I/O CIRCUITS AND MODELS - Advanced Signal Integrity for High-Speed Digital Design - page 456

high and the minimum signal that the receiver recognizes as the high logic
state. Conversely, the low-side noise margin, v NMl , is the difference between the
maximum output signal when driving low and the maximum signal recognized
by the receiver as the logic low state. Note from the figure that the receiver input
specs must comprehend variations in the signal levels caused by variability in
the fabrication process. Mathematically, the noise margins are expressed as

v NMl = v il, min − v ol, max (11-3a)

v NMh = v oh, min − v ih, max (11-3b)

11.3.2 Modeling

The CMOS inverter presents a high impedance to the input signal, limited only by
the input capacitance of the gate. As such, we typically model a CMOS receiver
as a simple capacitance to ground.

11.3.3 Advanced design considerations

Though the relatively large swing results in high noise margins, voltage mode
signaling systems possess multiple noise sources that degrade the noise immunity
of the system [Dally and Poulton, 1998]. For example, process variations such
as device thresholds and transconductance can cause inverter thresholds to vary
by more than 10% of the signal swing ( > 20% if supply voltage variation is
included), a phenomenon known as receiver offset . Other sources include power
supply noise, crosstalk, reflections, and transmitter offset.
These effects may be countered by designing additional noise tolerance into
the receiver through hysteresis. An example is a Schmitt trigger, which we show
in Figure 11-14a [Wang, 1989]. The MP 1 /MN 2 and MP 3 /MN 4 transistors form a
sequential pair of inverters. The hysteresis is created by feeding the output v out
back to the gates of MP 5 and MN 6 , which shifts the voltage transfer characteristic,
making it more difficult for a noise pulse to put the circuit into the keep-out zone,
as Figure 11-14b shows.

11.4 ESD PROTECTION CIRCUITS

Transceiver designs include electrostatic discharge (ESD) protection circuits to
prevent catastrophic failure due to breakdown of the MOSFET gates of the I/O
and core circuits. ESD damage can occur at any point during the manufacture,
assembly, test, and operation of a silicon chip, including handling and transport.
An example would be a technician wearing rubber-soled shoes on a test floor. The
insulating characteristics of the rubber can cause the technician to accumulate a
substantial static charge, which may discharge into any component with which he
or she may come into contact, damaging the component. An example ESD event