I/O CIRCUITS AND MODELS - Advanced Signal Integrity for High-Speed Digital Design - page 443

process transconductance (A/V 2 ) where k =

W = device width ( m)

µ

L = gate length ( m)

µ

v GS = potential difference between the transistor gate and source nodes

(V)

v T = transistor threshold voltage (V)

v DS = potential difference applied across the source and drain (V)

λ =

·

channel length modulation parameter (V m)

The process transconductance is

µε ox
t ox

k = (11-2)

where µ is the device mobility (m 2 /V s), ε ox the oxide permittivity (F/m), and

t ox the oxide thickness (m). The oxide permittivity ε ox is equal to 3.97 ε 0 , and
the oxide thickness

·

m process. Equation
(11-1) describes three distinct regions of operation. In the subthreshold region,
where v GS − v T

t ox is 5.7 nm for the MOSIS 0.25- µ

≤

0, the device conducts only a very small amount of leakage
current. In the triode region, the relationship between the device current and the
drain-source potential is approximately linear. In the saturation region, the device
enters a high-impedance state, acting like a (nearly) constant current source.
Figure 11-2 shows i D versus v DS curves for various gate-source potentials
( v GS ) that were created from HSPICE simulation using the SPICE level 3 model
for the MOSIS 0.25- m process that is contained in Appendix F. The dimensions

of the devices used to produce the figure are a width W of 222

µ

m and length L

µ

equal to 1 m for the PMOS

transistor. In the case of the PMOS device, v DS is less than zero since v out is less
than V DD . As a result, the current flows from the supply (source) to the drain,
so that i D is also less than zero. For the NMOS transistor, the polarities for v DS
and i D are both positive. Note from the figure that positive current is defined
as flowing back into the transistor device. We follow this convention throughout
this chapter, although it is equally valid to define positive current flowing in the
opposite direction, as long as consistency is maintained.
The voltage transfer characteristic of the inverter shown in Figure 11-3a was
created from HSPICE simulation using a SPICE level 3 model for the MOSIS
0.25-

m for the NMOS transistor and W/L = 845 m/1

µ µ µ

m process with device dimensions identical to those in Figure 11-2. The
figure shows how the output signal varies as a function of the input signal level.
When the input signal v in is at ground ( V SS ), the NMOS transistor, MN2, does
not conduct current, while the PMOS device, MP1, conducts current accord-
ing to equation (11-1). As a result, the output signal v out is pulled up to V DD
(2.5 V for the 0.25-

µ

m process) through MP1. As the input is raised to V DD ,
the output drops to ground. At approximately one-half of V DD , the inverter
enters a high-gain region in which v out changes rapidly as a function of v in .

µ