Digital Signal Processing Reference
In-Depth Information
onto the driver, receiver, transmission lines, reference planes, or clock circuits
will degrade the ideal relationship between the transmitted waveform and
v
ref
.
If the magnitude of the noise is large enough, the incorrect digital states will be
latched into the receiver, and bit errors will occur. Figure 7-1 depicts how noise
can make the determination of a logic 0 or 1 uncertain.
Power
noise
Ground
noise
v
ref
Receiver latch
Driver latch
Z
o
=
50
Ω
Data
from
CPU
Comparator
Q
D
D
Q
Z
o
=
50
Ω
Crosstalk noise
Clock
Clock
A
Z
o
=
50
Ω
Ideal received bit
(State
=
1)
Received bit with noise
(State is uncertain)
v
ref
v
ref
Time
Time
Figure 7-1
How system noise can severely degrade signal integrity on single-ended
buses. The ideal versus noisy receiver voltages compared to the reference voltage.
Driver latch
Receiver latch
Z
o
=
50
Ω
D
+
Q
Data
from
CPU
Diff Amp
D
Q
D
Q
Z
o
=
50
Ω
D
−
Clock
Clock
D
+
D
−
Time
Time
Figure 7-2
Differential signaling where each bit is transmitted from the driver to a
receiver using a pair of transmission lines driven in the odd mode. The signal is recovered
at the receiver with a differential amplifier.
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