Digital Signal Processing Reference
In-Depth Information
l
2
z
0
l
1
v
s
Receiver 1
R
s
=
Z
0
z
0
l
3
z
0
0-2
V
Receiver 2
T
3
T
2
Γ
1
Γ
2
Γ
3
Γ
4
Γ
5
0
250
ps
a
a
a
g
b
c
d
e
f
500
ps
A
b
B
750
ps
y
1000
ps
Figure 3-35
Lattice diagram of a T-topology when the leg lengths are not equal.
end of the long line (receiver 2). The initial voltage step launched onto line 1 is
Z
0
50
v
i
=
v
s
+
R
s
=
·
50
=
2
1
Z
0
50
+
The reflection and transmission coefficients looking from line 1 into the junc-
tion is
(Z
0
/
2
)
−
Z
0
(Z
0
/
2
)
+
Z
0
25
−
50
1
3
2
=
=
50
=−
25
+
2
3
Consequently, the initial voltage launched into both legs (lines 2 and 3) is
=
+
2
=
T
2
1
2
3
This voltage (
v
a
) travels down each leg and doubles when it arrives at the open
circuit (
4
v
a
=
T
2
v
i
=
=
5
=
1
)
. Therefore, the voltage at receiver 1 (
v
α
) occurs at
t
=
375
ps, which is the delay of line 1 plus line 2 (the short leg).
2
3
v
α
=
v
a
+
v
b
=
v
b
=
v
a
4
=
4
3
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