Graphics Programs Reference
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is marked with one token, then another token must be in either CPUidle
or useCPU; when one token is put in place removeCPU another token is
eventually deposited in place releaseCPU; finally if place releaseCPU is
marked then necessarily a token is present in either stoppedW or stoppedI.
The computation of the ECSs that are needed for the correct specifica-
tion of the immediate transition weights identifies the following pairs of
immediate transitions: (complete, I/O) and (getCPU, stopI). Transitions
getCPU and stopI are obviously in conflict since they share CPUidle as an
input place. Also transitions stopI and stopW share an input place (place
grabCPU), but they are not part of the same ECS since they are mutually
exclusive, as we already observed before, due to the token count of the P-
invariant useCPU + CPUidle + removeCPU + releaseCPU. This property
is identified by the MME condition (see Section 2.5.2) and is used to prop-
erly define the ECSs of the GSPN system. A further analysis of the way the
interruption subnet works allows us to notice that the weights associated
with transitions getCPU and stopI are actually inessential for the evolution
of the GSPN. Indeed, assume that both transitions are enabled and thus
that a token is present in place CPUidle. It is easy to show that this token
will be removed from the place and that another token will eventually ap-
pear in place removeCPU independently of the weights associated with the
conflicting transitions getCPU and stopI. If stopI wins the race against
getCPU a token is immediately deposited in place removeCPU; if how-
ever the race is won by transition getCPU, one token is first deposited in
place useCPU, but at this point transition stopW becomes enabled, which
yields again a token in place removeCPU, leaving both places useCPU and
grabCPU empty.
A complete structural analysis of the GSPN system of Fig. 7.3 allows an
informal demonstration that the model correctly represents the system we
intend to study. The same structural analysis can also be used to observe
that when place stoppedW is marked, place stoppedI is not, and vice-versa.
It thus follows that one of these two places can be removed from the net
and that its effect can be reproduced by the introduction of an inhibitor
arc. The GSPN system of Fig. 7.4 is equivalent to that of Fig. 7.3 with the
advantage of a simpler graphical representation.
7.1.2
CPU memory policies
When an interrupt occurs while the CPU is in use, different possibilities
must be considered with respect to the amount of work already performed
for the interrupted job before the interruption occurred. On the one hand
it may be reasonable to assume that if the interruption is due to a higher
priority task that needs immediate attention, the work already performed
for the interrupted job should not be lost; on the other hand, if the inter-
ruption corresponds to a CPU failure, it is likely that the work performed
 
 
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