Graphics Programs Reference
In-Depth Information
reachability graph is finite and the corresponding Markov chain has a fi-
nite state space. Following again the algebraic techniques of Chapter
2,
two
T semi-flows are computed (TS
1
= TERM + getCPU + CPU + complete
and TS
2
= getCPU + CPU + I/O + getDISK + DISK) that include all
the transitions of the GSPN model. The first T semi-flow corresponds to
the sequence of transitions that bring the GSPN back to its initial marking
without using the I/O. The second is a sequence of transitions that cannot
be fired from the initial marking. However, the sum of the two T semi-flows
yields a transition sequence that can be fired from the initial marking and
that brings the GSPN back to such a marking. Finally, using the conditions
discussed in Chapter
2,
it is possible to identify three Extended Conflict
Sets. Two of them are “degenerate” as they consist of one transition only
(immediate transitions getCPU, and getDISK, respectively); the third is
instead a proper ECS since it corresponds to the free-choice conflict between
the immediate transitions complete and I/O and for which a set of weights
must actually be defined.
Starting from this example, additional features of the system can be easily
studied with the associated GSPN system considering, for instance, the pos-
sibility for the CPU to break down or to be interrupted by higher priority
tasks.
7.1.1
CPU interruptions
Focusing our attention on the effect that these two phenomena may have
on the customers using the Central Server System, we can represent these
two different cases by adding a simple subnet that models the CPU in-
terruption. Figure
7.2
represents the interruption cycle of a high priority
external task. This task operates locally without any CPU need for a cer-
tain amount of time (token in place noINT) and occasionally requests the
CPU when transition INT fires. The action of acquiring the CPU (token
in place grabCPU) is performed by two mutually exclusive events imple-
mented by immediate transitions stopW and stopI that reflect the fact that
when the interruption occurs the CPU can either be working on regular
jobs or idle. The state of the CPU prior to the interruption is recorded by
alternatively marking places stoppedW and stoppedI to allow the situation
to be re-established at the end of the interruption. The CPU remains busy
while working on the high-priority task and then becomes again available
when timed transition CPUbusy fires followed by the firing of one of the two
immediate transitions returnW and returnI. In this model, the dynamics
of the interrupting phenomena are represented in a very abstract manner
by simply considering the frequency of the interruptions and the lengths of
their effects on regular customers.
The modified Central Server Model in which CPU interruptions may take
place at any point in time is obtained by merging places CPUidle and
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