Image Processing Reference
In-Depth Information
A
B
AB+AC+BC
C
Fig. 4.5 The implementation of the majority gate using QCA cells
The inverter is constructed with a fork structure [62] and its design is shown in
Fig. 4.6. The input A (in this example A
0) is fed at the left cell and is transmitted
by electrostatic forces between the electrons to the upper and the lower cells of the
design. The second last cell is properly placed in order to change the state of A .In
this example the second last cell, due to the electrostatic forces of its two previous
cells, will get the state of “1”. In general, it will be A which is the inversion of the
input A .
The AND and OR logic gates can be implemented as special cases of the majority
gate. When in a majority gate one of the inputs is steadily set to 0, then this gate
operates as the AND gate. As it is shown in Fig. 4.7 the design has the remaining
two inputs A and B and the outcome will always be their logic AND, symbolized as
AB .
When in a majority gate one of the inputs is steadily set to 1, then this gate
operates as the OR gate. As it is shown in Fig. 4.8 the design has the remaining two
inputs A and B and the outcome will always be their logic OR, symbolized as A
=
B .
More logic gates and circuits have been proposed in the literature such as XOR
gates [62], bit-serial adder, full adder [7, 12, 24, 39], multiplier [7], multiplexer [34,
+
A
A
Fig. 4.6 The implementation of the inverter using QCA cells
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