Cellular Automata for Image Resizing - Cellular Automata in Image Processing and Geometry - page 40

way to overcome the limitations on embedded systems is through customization. A
custom-made FPGA can combine (the advantages of a conventional computer with
those of an embedded processor, meaning the computational efficiency and energy
consumption, respectively).The main drawback of this option lies on the design and
the technical specifications of the specialized microprocessor. However, due to their
simplicity and repeatability, designing a custom FPGA system for a CA model re-
quires the formation of a single, simple cell and the connections to its neighbors.
In more detail, CA are probably the most suitable structures that best match to a
complete parallelized hardware implementation. In contrast to serial computers, the
motivation of model's hardware implementation is detected on the parallel process-
ing capacity of CA. It is an intrinsic feature that contributes to further accelerate the
model's operation. The FPGA based CA hardware implementation presents advan-
tages of low-cost, portability and unified and repeated structure. General purpose
computers provide sufficient processing power in the analysis of complicated phe-
nomena. Nonetheless, such an option may be prohibited or even impossible due to
high power consumption. Portable general purpose computers can be unable to han-
dle more complicated computational processes. A possible acceleration of a model's
execution can be achieved in such embedded systems provided that available fea-
tures of FPGA structures are utilized. These structures enable parallel data process-
ing using standardized digital modules. Besides, the circuitry of a CA demands the
design of a single cell and the rest of the configuration is the same across. The total
mask for a large CA pattern (cells, internal connections and cells interconnections)
could be generated by a simple repetitive procedure, thus preventing from silicon's
area overhead and long interconnection lines. Furthermore, due to the local pro-
cessing character, the length of the critical interconnections is minimized and it is
independent of the total number of cells.
As a result, the presented CA based image resizing method has been implemented
with the use of VHDL code in a single FPGA device. The discrimination between
the homogenous pixels and the edge pixels is achieved by the application of the
Canny edge detector which was also embedded in the tested FPGA platform as
the initial processing stage. The resulted map is typically increased in order for the
cells with the unknown pixel's light intensity value to be produced. Each cell of
the resulting CA grid receives as inputs all of its neighboring current states, and
it is further supplied with a clock, a start/stop and a reset signal. The cell outputs
after the application of the aforementioned transition rules result to all of its next
step states. All light intensity values are determined during the remapping process
based on the state of each corresponding cell. The process is repeated separately for
each one of the RGB channels. Moreover, the data output of the proposed hardware
implementation is made in a semi-parallel manner [9, 15, 29]. Essentially, instead
of providing the output data for each cell simultaneously on its own output, the
cells are grouped by column and the output of the n cells of each column appear
serially on the output bus that corresponds to the column. The adoption of such an
initialization method considerably shortens the number of input pins as well as the
length of interconnections, thus accelerating the operation of the resulting FPGA
processor.