Hardware Reference
In-Depth Information
Another specification to consider that is related to speed is the
CAS (column address
strobe) Latency
, which is often abbreviated as
CL
. This is also sometimes called
read
latency
,andit'sthenumberofclockcycles occurringbetween theregistration oftheCAS
signal and the resultant output data, with lower numbers of cycles indicating faster (bet-
ter)performance.Ifpossible,choosemoduleswithalowerCLfigurebecausethemother-
board chipset reads that specification out of the SPD (serial presence detect) ROM on the
module and takes advantage of the lower latency through improved memory controller
timings.
The following sections look at these memory types in more detail.
Fast Page Mode DRAM
Standard DRAM is accessed through a technique called
paging
. Normal memory access
requires that a row and column address be selected, which takes time. Paging enables
faster access to all the data within a given row of memory by keeping the row address the
sameandchangingonlythecolumn.Memorythatusesthistechniqueiscalled
Page Mode
or
Fast Page Mode memory
.OthervariationsonPageModewerecalledStaticColumnor
Nibble Mode memory.
Paged memory is a simple scheme for improving memory performance that divides
memory into pages ranging from 512 bytes to a few kilobytes long. The paging circuitry
then enables memory locations in a page to be accessed with fewer wait states. If the de-
