Hardware Reference
In-Depth Information
Several hidden buses exist on modern motherboards—buses that don't manifest them-
selves in visible slots or connectors. I'm talking about buses designed to interface chipset
components, such as the Hub Interface, the HyperTransport interface and the LPC bus.
The Hub Interface is a quad-clocked (4x) 66MHz 8-bit bus that carries data between the
MCH and ICH in hub architecture chipsets made by Intel. It operates at a bandwidth of
266MBps and was designed as a chipset component connection that is faster than PCI
yet uses fewer signals for a lower-cost design. Some recent workstation/server chipsets
and the latest 9-series desktop computer chipsets from Intel use faster versions of the hub
interface. The most recent chipsets from major third-party vendors also bypass the PCI
bus with direct high-speed connections, the most common of which is HyperTransport,
between chipset components.
See
“
Traditional North-South Bridge Architecture
,
”
p.
174
(this chapter).
In a similar fashion, the LPC bus is a 4-bit bus that has a maximum bandwidth of
16.67MBps; it was designed as an economical onboard replacement for the ISA bus. In
systems that use LPC, it typically connects Super I/O chip or motherboard ROM BIOS
components to the main chipset. LPC is faster than ISA yet uses far fewer pins and en-
ables ISA to be eliminated from the board entirely.
The system chipset is the conductor that controls the orchestra of system components, en-
abling each to have its turn on its respective buses.
Table 4.54
shows the widths, speeds,
data cycles, and overall bandwidth of virtually all PC buses in use today.
Table 4.54 Bandwidth (in MBps) and Detailed Comparison of Most PC Buses and Interfaces
