Hardware Reference
In-Depth Information
•
VIA
—VIA created the V-Link architecture to connect its North and South Bridge
chips at speeds matching or exceeding Intel hub architecture. V-Link uses a dedicated
8-bit data bus and is currently implemented in three versions: 4x V-Link, 8x V-Link,
and Ultra V-Link. 4x V-Link transfers data at 266MBps (4×66MHz), which is twice
the speed of PCI and matches the speed of Intel's AHA and HI 1.5 hub architectures.
8x V-Link transfers data at 533MBps (4×133MHz), which is twice the speed of Intel's
AHA interface. Ultra V-Link transfers data at 1GBps.
•
SiS
—SiS's MuTIOL architecture (also called
HyperStreaming
) provides performance
comparable to VIA's 4x V-Link; the second-generation MuTIOL 1G used in more re-
centSiS'schipsetsprovidesperformancecomparabletoVIA'sUltraV-LinkandIntel's
DMI architectures. Chipsets that support MuTIOL use separate address, DMA, input
data, and output data buses for each I/O bus master. MuTIOL buffers and manages
multiple upstream and downstream data transfers over a bidirectional 16-bit data bus.
•
ATI
—ATI (now owned by AMD) used a high-speed interconnect called A-Link in its
9100-series IGP integrated chipsets. A-Link runs at 266MBps, matching Intel's AHA
interface as well as first-generation V-Link and MuTIOL designs.
HyperTransport
HyperTransport, introduced in 2001 by the HyperTransport Technology Consortium
(
www.hypertransport.org
)
,has become the leading processor/chipset interconnect techno-
logy for non-Intel chipsets.
HyperTransporttransmitspacketsusingaDDRconnection(sendingontherisingandfall-
ing edges of the clock signal) between the CPU, memory, and the chipset. 64-bit AMD
desktop and most chipset implementations use a single 16-bit link, whereas 64-bit AMD
server processors such as the Opteron support up to three 16-bit links. HyperTransport is
used both with dual-chip chipsets and with single-chip chipsets developed by AMD and
NVIDIA.
Table 4.9
lists HyperTransport versions and speeds.
Table 4.9 - HyperTransport Versions
