Hardware Reference
In-Depth Information
The third motherboard component, the Super I/O chip, is connected to the 8MHz ISA bus
or the low pin count (LPC) bus and contains all the standard peripherals that are built
into a motherboard. For example, most Super I/O chips contain the serial ports, parallel
port, floppy controller, and keyboard/mouse interface. Optionally, they might contain the
CMOS RAM/clock, IDE controllers, and game port interface as well. Systems that integ-
rate IEEE 1394 and SCSI ports use separate chips for these port types.
Most recent motherboards that use North/South Bridge chipset designs incorporate a
Super-South Bridge, which incorporates the South Bridge and Super I/O functions into a
single chip.
Hub Architecture
Beginning in 1999, chipsets from Intel began using hub architectures in which the former
North Bridge chip is now called a Memory Controller Hub (MCH) or an I/O Hub (IOH)
and the former South Bridge is called an I/O Controller Hub (ICH). Systems that include
integratedgraphicsuseaGraphicsMemoryControllerHub(GMCH)inplaceofthestand-
ard MCH. Rather than being connected through the PCI bus as in a standard North/South
Bridge design, they are connected via a dedicated hub interface that is at least twice as
fast as PCI. The hub design offers several advantages over the conventional North/South
Bridge design:
•
It's faster
—The Accelerated Hub Architecture (AHA) interface that the 8xx series
uses has twice the throughput of PCI. The 9xx and newer series chipsets use an even
fasterversioncalledDMI(DirectMediaInterface),whichis7.5to14timesfasterthan
PCI.
•
Reduced PCI loading
—The hub interface is independent of PCI and doesn't share or
steal PCI bus bandwidth for chipset or Super I/O traffic. This improves performance
of all other PCI bus-connected devices because the PCI bus is not involved in these
transactions.
•
Reduced board wiring
—The AHA interface is 8 bits wide and requires 15 signals to
be routed on the motherboard, whereas DMI is 4 bits wide and requires 8 differential
pairs of signals. By comparison, PCI requires that no fewer than 64 signals are routed
on the board, causing increased electromagnetic interference (EMI) generation, great-
er susceptibility to signal degradation and noise, and increased board manufacturing
costs.
This hub interface design allows for a much greater throughput for PCI devices because
there is no South Bridge chip (also carrying traffic from the Super I/O chip) hogging
the PCI bus. Due to bypassing PCI, the hub interface also enables greater throughput for
