Hardware Reference
In-Depth Information
core speed cache in later Athlon XP models. All PGA Socket A versions have the full-
speed cache. The Athlon also supports MMX and the Enhanced 3DNow! Instructions.
The initial production of the Athlon used 0.25-micron technology, with newer and faster
versionsbeingmadeon0.18-micronand0.13-micronprocesses.Laterversionswerebuilt
using copper metal technology, a first in the PC processor business.
In most benchmarks, the AMD Athlon is equal, if not superior, to the Intel Pentium III.
AMD also beat Intel to the 1GHz mark by introducing its 1GHz Athlon two days before
Intel introduced the 1GHz Pentium III.
AMD Duron
TheAMDDuronprocessor(originally code-named Spitfire) wasannounced inJune2000
and is a derivative of the AMD Athlon processor in the same fashion as the Celeron is a
derivative of the Pentium II and III. Basically, the Duron is an Athlon with less L2 cache;
allothercapabilitiesareessentiallythesame.Itisdesignedtobealower-costversionwith
less cache but only slightly less performance. In keeping with the low-cost theme, Duron
contains 64KBon-dieL2cache andisdesigned forSocket A,asocket versionoftheAth-
lon Slot A. Except for the Duron markings, the Duron is almost identical externally to the
Socket A versions of the original Athlon.
Essentially, the Duron was designed to compete against the Intel Celeron in the low-cost
PCmarket,justastheAthlonwasdesignedtocompeteinthehigher-endPentiumIIImar-
ket. The Duron has since been discontinued and replaced by the Sempron.
AMD Athlon XP
Asmentionedearlier,thelastoftheSocketA-basedAthlonprocessorsiscalledtheAthlon
XP. This is basically an evolution of the previous Athlon, with improvements in the in-
struction setsoitcanexecute IntelSSEinstructions andanewmarketing scheme thatdir-
ectly competed with the Pentium 4. Athlon XP also adopted a larger (512KB) full-speed
on-die cache.
AMD uses the term
QuantiSpeed
(a marketing term, not a technical term) to refer to the
architecture of the Athlon XP. AMD defines this as including the following:
•
A nine-issue superscalar, fully pipelined microarchitecture
—This provides more
pathways for instructions to be sent into the execution sections of the CPU and in-
cludes three floating-point execution units, three integer units, and three address cal-
culation units.
