Hardware Reference
In-Depth Information
• Superscalar parallel execution units (seven)
• Dynamic execution
• Branch prediction
• Speculative execution
•Large64KBL1cache(32KBinstructioncacheplus32KBwrite-backdual-porteddata
cache)
• Built-in floating-point unit
• Industry-standard MMX instruction support
• System Management Mode
• Ceramic pin grid array (CPGA) Socket 7 design
• Manufactured using 0.35-micron and 0.25-micron, five-layer designs
The AMD-K6 processor architecture is fully x86 binary code compatible, which means it
runs all Intel software, including MMX instructions. To make up for the lower L2 cache
performanceoftheSocket7design,AMDbeefeduptheinternalL1cacheto64KB,twice
the size of the Pentium II or III. This, plus the dynamic execution capability, enabled the
K6tooutperformthePentiumandcomeclosetothePentiumIIandIIIinperformancefor
a given clock rate.
There were two subsequent additions to the K6 family, in the form of the K6-2 and
K6-3. The K6-2 offered higher clock and bus speeds (up to 100MHz) and support for the
3DNow! instruction set. The K6-3 added 256KB of on-die full-core speed L2 cache. The
addition of the full-speed L2 cache in the K6-3 was significant because it enabled the K6
series to fully compete with the Intel Pentium III processor family, although it did cause
the processor to run hot, resulting in its discontinuation after a relatively brief period.
The original K6 has 8.8 million transistors and is built on a 0.35-micron, five-layer
process. The die is 12.7mm on each side, or about 162 square mm. The K6-3 uses a
0.25-micron process and incorporates 21.3 million transistors on a die only 10.9mm on
each side, or about 118 square mm.
AMD K7 Processors
TheAthlon,Duron,andAthlonXPareallmembersofAMD'sK7processorfamily,which
represented a clean break with AMD's previous plug compatibility with Intel processors.
Instead, AMD developed its own processor slot and socket design and became a serious
rival to Intel in both performance and price.
