Hardware Reference
In-Depth Information
Intel Core 2 Family
ThehighlyefficientCoremicroarchitecturedesignfeaturedintheCore2processorfamily
provides40%betterperformanceandis40%moreenergyefficientthanthepreviousgen-
eration Pentium D processor. It is also interesting to note that the Core 2 Duo processor is
Intel's third-generation dual-core processor; the first generation was the Pentium D pro-
cessorfordesktopPCs,andthesecondgeneration wastheCoreDuoprocessorformobile
PCs.
ThenamingofboththeCore2processorandtheCoremicroarchitectureissomewhatcon-
fusing because the Core name was also used on the Core Solo and Core Duo processors,
which were the successors to the Pentium M in Intel's mobile processor family. What is
strange is that the Core Solo and Duo do
not
incorporate Intel's Core microarchitecture,
and although they served as a developmental starting point for the Core 2, the Core Solo
and Duo are internally different and not in the same family as the Core 2 processors. Be-
causetheCoreSoloandCoreDuoprocessorsareconsideredmobileprocessorsonly,they
are not covered here.
The Core 2 was released as a dual-core processor, but since then quad-core versions have
alsobeenreleased.Thedual-coreversionsoftheCore2processorshave291milliontran-
sistors, whereas the quad-core versions have double that, or 582 million. They include
1MB or 2MB of L2 cache per core, with up to 8MB total L2 in the quad-core versions.
Initially, all were built on 300mm wafers using a 65nm process, but since then 45nm ver-
sions have been released as well.
The highlights of the Core microarchitecture include the following:
•
Wide dynamic execution
—Internal execution cores that are 33% wider than in pre-
vious generations, allowing each core to execute up to four full instructions simul-
taneously. Further efficiencies are achieved through more accurate branch prediction,
deeper instruction buffers for greater execution flexibility, and additional features to
reduce execution time.
•
Intelligent power capability
—An advanced power-gating capability that turns on in-
dividual processor subsystems only if they are needed.
•
Advanced smart cache
—A multicore optimized cache that increases the probability
that each execution core can access data from a shared L2 cache.
•
Smart memory access
—Includes a capability called memory disambiguation, which
increases the efficiency of out-of-order processing by providing the execution cores
with the intelligence to speculatively load data for instructions that are about to ex-
ecute.
