Hardware Reference
In-Depth Information
Branch Prediction
Branch prediction
is a feature formerly found only in high-end mainframe processors. It
enables the processor to keep the instruction pipeline full while running at a high rate of
speed. A special fetch/decode unit in the processor uses a highly optimized branch-pre-
diction algorithm to predict the direction and outcome of the instructions being executed
throughmultiple levelsofbranches,calls,andreturns.Itissimilartoachessplayerwork-
ing out multiple strategies in advance of game play by predicting the opponent's strategy
several moves into the future. By predicting the instruction outcome in advance, the in-
structions can be executed with no waiting.
Dataflow Analysis
Dataflow analysis
studies the flow of data through the processor to detect any opportunit-
ies for out-of-order instruction execution. A special dispatch/execute unit in the processor
monitors many instructions and can execute these instructions in an order that optimizes
the use of the multiple superscalar execution units. The resulting out-of-order execution
of instructions can keep the execution units busy even when cache misses and other data-
dependent instructions might otherwise hold things up.
Speculative Execution
Speculative execution
is the processor's capability to execute instructions in advance of
the actual program counter. The processor's dispatch/execute unit uses dataflow analysis
to execute all available instructions in the instruction pool and store the results in tempor-
ary registers. A retirement unit then searches the instruction pool for completed instruc-
tions that are no longer data dependent on other instructions to run or which have unre-
solved branch predictions. If any such completed instructions are found, the retirement
unit or the appropriate standard Intel architecture commits the results to memory in the
order they were originally issued. They are then retired from the pool.
Dynamic execution essentially removes the constraint and dependency on linear instruc-
tion sequencing. By promoting out-of-order instruction execution, it can keep the instruc-
tion units working rather than waiting for data from memory. Even though instructions
can be predicted and executed out of order, the results are committed in the original order
so they don't disrupt or change program flow. This enables the P6 to run existing Intel ar-
chitecturesoftwareexactlyastheP5(Pentium)andpreviousprocessorsdid—justawhole
lot more quickly!
Dual Independent Bus Architecture
The Dual Independent Bus (DIB) architecture was first implemented in the sixth-gener-
ation processors from Intel and AMD. DIB was created to improve processor bus band-
