Hardware Reference
In-Depth Information
The SSE
x
instructions are particularly useful with MPEG2 decoding, which is the stand-
ard scheme used on DVD video discs. Therefore, SSE-equipped processors should be
more capable of performing MPEG2 decoding in software at full speed without requiring
an additional hardware MPEG2 decoder card. SSE-equipped processors are also much
better and faster than previous processors when it comes to speech recognition.
One of the main benefits of SSE over plain MMX is that it supports single-precision
floating-point SIMD operations, which have posed a bottleneck in the 3D graphics pro-
cessing. Just as with plain MMX, SIMD enables multiple operations to be performed per
processor instruction. Specifically, SSE supports up to four floating-point operations per
cycle; that is, a single instruction can operate on four pieces of data simultaneously. SSE
floating-point instructions can be mixed with MMX instructions with no performance
penalties. SSE also supports data
prefetching
, which is a mechanism for reading data into
the cache before it is actually called for.
SSE includes 70 new instructions for graphics and sound processing over what MMX
provided. SSE is similar to MMX; in fact, besides being called KNI, SSE was called
MMX-2 by some before it was released. In addition to adding more MMX-style instruc-
tions, the SSE instructions allow for floating-point calculations and now use a separate
unit within the processor instead of sharing the standard floating-point unit as MMX did.
SSE2 was introduced in November 2000, along with the Pentium 4 processor, and adds
144 additional SIMD instructions. SSE2 also includes all the previous MMX and SSE in-
structions.
SSE3 was introduced in February 2004, along with the Pentium 4 Prescott processor, and
adds 13 new SIMD instructions to improve complex math, graphics, video encoding, and
thread synchronization. SSE3 also includes all the previous MMX, SSE, and SSE2 in-
structions.
SSSE3 (Supplemental SSE3) was introduced in June 2006 in the Xeon 5100 series server
processors, and in July 2006 in the Core 2 processors. SSSE3 adds 32 new SIMD instruc-
tions to SSE3.
SSE4 (also called HD Boost by Intel) was introduced in January 2008 in versions of the
Intel Core 2 processors (SSE4.1) and was later updated in November 2008 in the Core i7
processors (SSE4.2). SSE4 consists of 54 total instructions, with a subset of 47 instruc-
tions comprising SSE4.1, and the full 54 instructions in SSE4.2.
Advanced vector extensions (AVX)wasintroduced inJanuary2011inthesecond-general
Core i-series “Sandy Bridge” processors, and is also supported by AMD's new “Bull-
dozer” processor family. AVX is a new 256-bit instruction set extension to SSE, compris-
ing 12 new instructions. AVX helps floating-point intensive applications such as image
