Hardware Reference
In-Depth Information
MMX consists of two main processor architectural improvements. The first is basic: All
MMX chips have a larger internal L1 cache than their non-MMX counterparts. This im-
provestheperformance ofanyandallsoftwarerunningonthechip,regardless ofwhether
it actually uses the MMX-specific instructions.
The other part of MMX is that it extends the processor instruction set with 57 new com-
mands or instructions, as well as a new instruction capability called single instruction,
multiple data (SIMD).
Modernmultimediaandcommunicationapplicationsoftenuserepetitiveloopsthat,while
occupying 10% or less of the overall application code, can account for up to 90% of the
execution time. SIMD enables one instruction to perform the same function on multiple
piecesofdata,similartoateachertellinganentireclassto“sitdown,”ratherthanaddress-
ing each student one at a time. SIMD enables the chip to reduce processor-intensive loops
common with video, audio, graphics, and animation.
Intel also added 57 new instructions specifically designed to manipulate and process
video, audio, and graphical data more efficiently. These instructions are oriented to the
highly parallel and often repetitive sequences frequently found in multimedia operations.
Highly parallel refers to the fact that the same processing is done on many data points,
such as when modifying a graphic image. The main drawbacks to MMX were that it
workedonlyonintegervaluesandusedthefloating-pointunitforprocessing,sotimewas
lost when a shift to floating-point operations was necessary. These drawbacks were cor-
rected in the additions to MMX from Intel and AMD.
Intel licensed the MMX capabilities to competitors such as AMD and Cyrix, who were
then able to upgrade their own Intel-compatible processors with MMX technology.
SSE
In February 1999, Intel introduced the Pentium III processor and included in that pro-
cessor an update to MMX called Streaming SIMD Extensions (SSE). These were also
called Katmai New Instructions (KNI) up until their debut because they were originally
included on the Katmai processor, which was the code name for the Pentium III. The Cel-
eron 533A and faster Celeron processors based on the Pentium III core also support SSE
instructions. The earlier Pentium II and Celeron 533 and lower (based on the Pentium II
core) do not support SSE.
The Streaming SIMD Extensions consist of 70 new instructions, including SIMD floating
point, additional SIMD integer, and cacheability control instructions. Some of the techno-
logies that benefit from the Streaming SIMD Extensions include advanced imaging, 3D
video, streaming audio and video (DVD playback), and speech-recognition applications.
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