Hardware Reference
In-Depth Information
were supplied as complete packaged chips and not raw die, Intel mounted them on a cir-
cuit board alongside the processor. This is why the Pentium II was designed as a cartridge
rather than what looked like a chip.
One problem was the speed of the available third-party cache chips. The fastest ones on
the market were 3ns or higher, meaning 333MHz or less in speed. Because the processor
was being driven in speed above that, in the Pentium II and initial Pentium III processors,
Intel had to run the L2 cache at half the processor speed because that is all the commer-
cially available cache memory could handle. AMD followed suit with the Athlon pro-
cessor, which had to drop L2 cache speed even further in some models to two-fifths or
one-third the main CPU speed to keep the cache memory speed less than the 333MHz
commercially available chips.
Then a breakthrough occurred, which first appeared in Celeron processors 300A and
above. These had 128KB of L2 cache, but no external chips were used. Instead, the L2
cache had been integrated directly into the processor core just like the L1. Consequently,
both the L1 and L2 caches now would run at full processor speed, and more importantly
scaleupinspeedastheprocessorspeedsincreasedinthefuture.InthenewerPentiumIII,
as well as all the Xeon and Celeron processors, the L2 cache runs at full processor core
speed, which means there is no waiting or slowing down after an L1 cache miss. AMD
also achieved full-core speed on-die cache in its later Athlon and Duron chips. Using on-
die cache improves performance dramatically because 9% of the time the system uses the
L2. It now remains at full speed instead of slowing down to one-half or less the processor
speed or, even worse, slowing down to motherboard speed as in Socket 7 designs. Anoth-
er benefit of on-die L2 cache is cost, which is less because fewer parts are involved. L3
on-die caches offer the same benefits for those times when L1 and L2 cache do not con-
tain the desired data. And, because L3 cache is much larger than L2 cache (6MB in AMD
Phenom II and 12MB in Core i7 Extreme Edition), the odds of all three cache levels not
containing the information desired are reduced over processors which have only L1 and
L2 cache.Let's revisit the restaurant analogy using a 3.6GHz processor. You would now
betakingabiteeveryhalfsecond(3.6GHz=0.28nscycling).TheL1cachewouldalsobe
runningatthatspeed,soyoucouldeatanythingonyourtableatthatsamerate(thetable=
L1 cache). The real jump in speed comes when you want something that isn't already on
the table (L1 cache miss), in which case the waiter reaches over to the cart (which is now
directly adjacent to the table) and 9 out of 10 times is able to find the food you want in
just over one-quarter second (L2 speed = 3.6GHz or 0.28ns cycling). In this system, you
would run at 3.6GHz 99% of the time (L1 and L2 hit ratios combined) and slow down to
RAMspeed(waitforthekitchen)only1%ofthetime,asbefore.Withfastermemoryrun-
ning at 800MHz (1.25ns), you would have to wait only 1.25 seconds for the food to come
