Types of Image Sensors - Essential Principles of Image Sensors - page 70

Readout
pulse

p +

VCCD

PD

p -

n -type
substrate

Read
out

VCCD

p

p -

Discharge

p -well

Readout n -type substrate

Discharge

Depleted
potential

Electronic
shutter
pulse

V-sub
Different paths at discharge and readout

(b)

To deplete photodiode at both discharge and readout
Readout potential > Depleted potential > Discharge potential
(a)

Excess or deficiency of charges at each pixel causes FPN

Necessity of the same condition of PD just after
both operations

Depleted PD

→ Potential decision by PD itself

(c)

FIGURE 5.23
Schematic diagram of electronic shutter operation at the completely depleted PD in a VOD structure: (a) poten-
tial distribution; (b) paths for discharge and readout; (c) necessity of completely depleted PD.

MOS sensor. There is no similar problem. But the four-transistor pixel configuration in
the CMOS sensor has the same transfer operation as that of CCD, so complete transfer is
required at readout operation.
Looking at Figures 5.21 and 5.22, some readers might consider the transfer and move-
ment of electrons as analogous with water flow. But this is not correct. Water movement
is controlled by gravitation and surface tension. On the other hand, electron movement
is ruled by electric field and thermal energy. The two mechanisms are quite different.
Readers need to break away from the “water model” to understand this accurately.

5.1.2.3 Buried Photodiode / Pinned Photodiode

The structure of a buried PD 13 or pinned PD 16 was shown in Section 2.1.7, although the
functions were not discussed in detail. A PD can exist that is buried but not pinned, and
one that is pinned but not buried can also exist. Buried PDs are named after their structure,
while pinned PDs are so called because their potential is pinned by complete depletion.
A buried/pinned PD was proposed to prevent lag phenomena due to incomplete trans-
fer, which was seen in normal pn -junction PDs in early IT-CCDs. Therefore, their initial
purpose was to achieve a lag-free PD. The function of dark current suppression was not
strongly focused on, because dark current caused by pn -PDs was not a severe problem for
the level of CCDs at the time. So it is possible that the existence of lag phenomena incu-
bated buried/pinned PDs.
Before discussing this, let us consider the normal pn -junction PD shown in Figure 5.24.
There is a depletion layer at the junction of the n- and p- type impurity areas. It also exists
at the silicon surface, where interface states exist. These interface states mostly play the
role of stepping stone of thermally excited electrons from valence band to conduction
band, as shown in the energy diagram along the interface in Figure 5.24b; that is, charges