Image Processing Reference
In-Depth Information
RST
(reset
transistor)
V
dd
Pixel
Drive
transistor
RS
(row select
transistor)
Load
transistor
V
LG
V
ss
FPN cancellation circuit (CDS)
CS
(column select
transistor)
Output
Horizontal access circuit
FIGURE 5.43
Schematic diagram of a 3-Tr pixel configuration CMOS sensor.
Output
RS
Pixel
RST
V
dd
Drive
Tr
V
ss
V
LG
Light
Vertical
signal
line
Load
Tr
(a)
PD
1.
Exposure completion
0 V
Q
sig
RST: OFF
RS : OFF
3 V
Signal
output
voltage
2.
Signal output
0 V
Q
sig
RST: OFF
RS: ON
(b)
3 V
3.
Photodiode reset
0 V
RST: ON
Q
sig
RS: ON
3 V
Reset
output
voltage
4.
Reset output
0 V
RS: OFF
RS: ON
3 V
FIGURE 5.44
Operational diagram of one pixel in a 3-Tr configuration: (a) cross-sectional view; (b) operational diagram by
potential distribution.
