Hardware Reference
In-Depth Information
GPINTENx Register
This register enables interrupts on input pin events. Only inputs generate interrupts, so
any enable bits for output pins are ignored. How the interrupt is generated by the input is
determined by registers
DEFVALx
and
INTCONx
.
GPINTENx Register
GPIO
Address
Bit
7
6
5
4
3
2
1
0
A
0x04
R
Y
Y
Y
Y
Y
Y
Y
Y
B
0x05
W
Y
Y
Y
Y
Y
Y
Y
Y
Reset
0
0
0
0
0
0
0
0
GPINTENx Bit Value
0
Disable interrupts on this input
1
Enable interrupts for this input
For this project, we enabled interrupts on all inputs for ports A and B.
INTFx Register
This interrupt flags register contains the indicators for each input pin causing an
interrupt. This register is
unwritable
.
Interrupt service routines start with this register to identify which inputs are the
cause of the interrupt. The
DEFVALx
and
INTCONx
registers configure how those interrupts
are generated. The INTFx flags are cleared by reading the corresponding
INTCAPx
or
GPIOx
register.
INTFx Register
GPIO
Address
Bit
7
6
5
4
3
2
1
0
A
0x0E
R
Y
Y
Y
Y
Y
Y
Y
Y
B
0x0F
W
N
N
N
N
N
N
N
N
Reset
0
0
0
0
0
0
0
0
INTFx
Bit Value
0
No interrupt for this input
1
Input has changed or does not compare