Security of Safety Important I&C Systems - Nuclear Power Plant Instrumentation and Control Systems for Safety and Security - page 263

Figure 14. Criticality matrixes

Table 3. Results of IMECA for FPGA attacks

Row
Number

Attack
Mode

Countermeasures

1 Black Box Attack Complication of electronic design logic

2 Readback Attack The use of security bit.

Application of physical security controls

3 Cloning Attack Checking of chip's internal ID before powering up an electronic design.

Encoding of configuration file.
Storing of configuration file within FPGA chip (requires internal power source)

4 Physical Attack Decreasing memory retention effect.

Monitoring of parameters (voltage, temperature, clock) of environment and chip

5 Side-Channel Attack Addition of random noise in measurable parameters (or masking of information by random values).

Decrease of difference in power consumption.
Changing of electronic design logic

attack severity decreasing, and et is efficiency of
time to recovery decreasing. The total efficiency
is an integral value and can be calculated using
the following equation:

Correspondence between available counter-
measures and appropriate attacks can be specified
in a form of matrix, where the rows represent a set
of attacks possible due to I&C system's vulner-
abilities detected during its security assessment,
and the columns are represented by available
security countermeasures and their appropriate
effectiveness metrics. An example of such table
is represented below (see Table 4).
After application of (3), we can represent
Table 4 in a reduced form (see Table 5), which

e = ep + eh + et . (3)

Obviously those existing security counter-
measures are not completely all-purpose and
can be used for certain vulnerability or a set of
vulnerabilities.