Environmental Engineering Reference
In-Depth Information
•
Chip Packaging:
At this stage the tested
chip is mounted into the chip package (it
can also contain other hardware compo-
nents); from vulnerability point of view,
interfaces between all hardware compo-
nents introduce potential vulnerabilities at
this stage.
In general case, accordingly to Tehranipoor M.
et al., (Tehranipoor, M. et al., 2010), HTs can be
inserted into one or several system components.
In the latter case, each of HTs can operate inde-
pendently from other HTs, or together with other
HTs inside the system to perform group attack
on the system.
Depending on probable physical characteris-
tics, HTs can be differed by:
From abstraction level's point of view, HTs
can be inserted into a chip at the following levels:
•
Type
•
System Level:
Developers deine hardware
modules, interconnections and communi-
cation protocols, which can determine HT
activation character.
•
Development Environment:
It can be
characterized by application of tools for
design synthesis, simulation, veriica-
tion, and validation; such tools can be a
source of HTs in the design and, moreover,
contain software trojans for hiding inserted
HTs.
•
RTL Level:
Is easily vulnerable by HTs,
as at this level each functional module is
described in terms of registers, signals and
Boolean functions.
•
Size
•
Structure
•
Location
According to the type, HTs can be:
•
Functional (implemented through addition
or a removal of logic elements).
•
Parametric (implemented through modii-
cation of a existing logic or connections).
According to location, HTs can directly affect
the following components:
• Processor (HTs can modify an order of in-
structions execution).
• Memory, including its interfaces (HTs can
modify values, stored in a memory, and
also block reading/writing operations for
certain memory areas).
•
Level of Logic Elements:
A chip is repre-
sented as interconnection of logic elements
that allows controlling all aspects of insert-
ed HTs, including size and location.
•
Level of Transistors:
Logic gates are built
from transistors, allowing managing difer-
ent chip characteristics (for example, time
characteristics and power consumption);
addition or removal of individual transis-
tors allows modifying chip functionality,
and modiication of transistor sizes lead to
modiication of chip parameters.
•
Input-output system (HTs can be located
in peripherals of chip or device, as well
as within printed circuit board, and, inter-
acting with external components, control
communications between a processor and
external components of a system).
•
Power circuitry (HTs can alter voltage and
current supplied to chip or device, causing
failures).
•
Physical Level:
This level describes all
chip components, their physical size and
location, that allows inserting HTs, for ex-
ample, by modifying wire size, a distance
between circuit elements or reassigning
metal layers.
•
Clock circuitry (HTs can change clock's
frequency, supplied to diferent functional
modules, causing faults inside the system,
containing such modules).
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