Environmental Engineering Reference
In-Depth Information
signatures and a task of their processing for
obtaining required results. Tasks of collect-
ing and processing of such information are
rather nontrivial, however, there are known
complex techniques requiring only several
measurements to attack a system.
• Addition of unintended functionality (for
example, by development tools).
Stealing of intellectual property.
So, it is possible to identify a number of factors
that can cause vulnerabilities at different stages
of FPGA chip life cycle (see Figure 6), including:
Data Analysis: It is a logical continuation of
read-back attack or side-channel attack, as data,
obtained from these attacks, are considered as
noise. The fact that an adversary has obtained
such data does not guarantee a possibility of
recovering original FPGA electronic design, but
makes it probable.
Logically following stage after the read-back
attack (or cloning attack) is Reverse Engineer-
ing. It allows, for example, discovering a data
structure, used by the manufacturer, decrypting
FPGA configuration. Reverse Engineering is not
limited to discovering of FPGA configuration, but
also can be achieved by observing bus activities
during program execution in a softcore processor
implemented in FPGA environment. Application
of the reverse engineering technique is character-
ized by quite high percentage of its successful
completion.
To retrieve data, an adversary can use ap-
proaches based either on Simple Power Analysis
or Differential Power Analysis techniques. These
approaches are based on device's energy consump-
tion analysis, while performing cryptographic
operations, depending on time and their identifi-
cation with the known templates. So, a success of
the attack directly depends on time and number
of stored statistic data.
As of today, a number of factors that can cause
FPGA vulnerabilities, which can be used in cyber
attacks, should be identified. Such attacks can
result in:
• A stage of FPGA chip design.
• A stage of its manufacturing and packaging.
• A stage of development of FPGA elec-
tronic design (which describes application
logic) for implementation to FPGA chip.
• A stage of FPGA electronic design
implementation.
• A stage of operation of FPGA-based
device.
Such factors are the following:
• Use of malicious tools (EDA tools, CAD
tools) during chip designing by a vendor
and during FPGA electronic design devel-
opment by an application designer for such
chip;
• Use of compromised devices during inte-
gration of FPGA electronic design by an
application designer;
• Use of IP-cores from third-party vendors in
FPGA electronic design;
The presence of adversaries (insiders) in-
side the development team.
To decrease number of FPGA potential vul-
nerabilities, FPGA chip vendors should solve the
following tasks:
To provide protection of own design and
technology against reverse engineering,
copying or modiication.
• Hardware modiication, reading and/
or distortion of conidential and/or criti-
cal information (for example, through
side-channels).
To provide the customers with design se-
curity means during development and op-
eration FPGA-based devices.
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