Field Programmable Gate Array Technology for NPP I&Cs - Nuclear Power Plant Instrumentation and Control Systems for Safety and Security - page 133

• Positive testing results of all new function-
al blocks and algorithm program models in
CASE-tools environment applied.
• Equivalence of developed algorithm pro-
gram models and protective signal forma-
tion algorithm block-diagrams as veriied
at previous stage.
• Absence of any input, output signals and/
or set points in FPGA electronic design
model for which inputs and/or outputs ex-
ist in none of algorithm program models.

• Detailed analysis of components in each
class.
• Filling of traceability matrix with input
data by systematization of components in
each class.
• Analysis of veriication stage output data
presentation and separation of component
classes.
• Conformity analysis between input and
output data and illing of traceability ma-
trix with output data by comparison of
each of output data component and input
data components.
• Analysis of inal traceability ma-
trix, formulations of conclusions and
recommendations.
• Overpatching and correction of inal prod-
uct in case any discrepancies are found be-
tween input data and output result of devel-
opment stage.

Conformity of FPGA with implemented pro-
gram model to this program model in CASE-tools
environment is assessed by comparison of signal
formation conditions and timing characteristics as
obtained by testing to logic conditions, numeri-
cal values of set points and timing characteristics
specified in algorithm block-diagrams and “hard
copies” from screen that diagrammatically reflect
the developed FPGA logic structure program
model.
Conformity criteria for this verification stage
are:

Let us prepare a formal description of FPGA
electronic design traceability analysis.
FPGA electronic design is developed and
verified in 4 stages, with traceability analysis per-
formed for each stage. Assume FPGA realizing N
signal processing algorithms. For each algorithm
S classes of omponents exist that belong to FPGA
algorithm as well as L input components Аij of
FPGA algorithm and M output components Bij
of FPGA algorithm that belong to i-th class. Our
analysis shows that component classes of FPGA
algorithms are equivalent for each development
class. Between all input and output algorithm
component we must ascertain whether equivalence
conformity is met or not. In this context traceability
analysis would be successful if each of input ele-
ments corresponds to one or more output elements
and each of output elements corresponds to one
or more input elements:

Successful implementation of FPGA electronic
design that was verified at previous stage
into FPGA-chip.
Equivalence of output signal formation conditions
and timing characteristics as obtained by
testing to logic conditions, numerical values
of set points and timing characteristics of
FPGA electronic design that was verified at
previous stage.

Thus, FPGA electronic design traceability
analysis method for each verification stage in-
cludes such actions:

• Analysis of veriication stage input data
presentation and separation of component
classes (signals, communication

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lines,

( ∀ A : ∃ B , A ⇔ B ) ∨ ∀ ( B :

ij ij ij ij ij

(1)

nodes, functional blocks, etc.)

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∃ A , B ⇔ A . )

ij ij ij