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of program model outputs and/or of established
control points within the program model as caused
by such effects are observed at instrumental screen
and registered as “hard copies” from the screen.
Under timing simulation consecutive state altera-
tions at one of program model inputs are imitated
in turns and altered states of test outputs (“timing
diagrams”) and/or of established control points
within the program model are monitored.
Tests performed should imply:
Walk-through Method of Documentation
Viewing Used to Assess Testing Completeness:
Walk-through of documentation is a kind of in-
spection of documents correctness, completeness
and consistency. We shall mark the peculiarities
of one of the key stages - analysis of testing
complete coverage of algorithm program models
in the process of FPGA-project verification. Such
analysis is performed by comparison between the
list of qualitatively different combinations of input
states and/or of their alterations that cause altered
output states and the list of program model input-
output states that are imitated and monitored in
the course of testing.
Criteria of conformity in this are:
•
Testing of new functional blocks (IP-
Cores), arranged from typical functional
elements in CASE-tools environment.
•
Testing of algorithm block-diagram pro-
gram models arranged from typical func-
tional elements and new functional blocks
in design environment.
•
Presence and completeness of tests for all
new functional blocks composed from typ-
ical functional elements.
•
Testing of integrated algorithm block-dia-
gram program model arranged from signal
formation algorithm block-diagram pro-
gram models in CASE-tools environment.
•
Presence and completeness of tests for all
FPGA-project algorithm program models.
•
PRESENCE AND COMPLETENESS OF
TESTS FOR INTEGRATED PROGRAM
MODEL.
New functional blocks are tested directly
in CASE-tools environment. As the functional
blocks are invariant relative to input data, after
verification they may be included into the library
of CASE-tools applied and find multiple usages
during development of FPGA-projects. Tests
for algorithm program models are developed on
the basis of signal formation algorithm block-
diagrams verified at the previous stage.
Tests for integrated program model are devel-
oped on the basis of signal formation algorithm
program models verified at the previous stage.
The developed tests and testing results must
be presented in FPGA-project verification docu-
ments in the form of tables and timing diagrams.
In timing diagrams the imitated input states (in-
put signals) of program models in CASE-tools
environment, their alterations and altered states
of each of outputs should be specified.
Criterion of success is a conclusion that test
results correspond to expected results.
•
Presence and completeness of tests for inal
FPGA with implemented program model.
Blackbox Functional Testing Method:
Func-
tional testing, named also blackbox testing,
consists in experimental checking of functions
performed by a programmable component with
implemented program model to define their con-
formity to system requirements, signal formation
algorithm schemes and user documentation (Scott,
J., Lawrence, J., 1994).
Traceability Analysis:
This is done to ensure
that input requirements of a certain process are
exhaustively considered by analysis of their con-
nections to output results as well as all require-
ments have been defined and brought through the
life cycle of development, i.e. from requirement
analysis up to final testing.
Traceability analysis includes identification
of input requirements and confirmation of the
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