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of software product development in a problem
oriented program language using specialized tools.
An alternative to direct diagram drawing may
be FPGA structure description in a HDL, such as
Verilog or VHDL.
HDL is a formalized record that may be used
at all development stages. System function is de-
fined as transformation of input values into output
values, operation time in this transform being pre-
scribed in explicit form. General FPGA structure
is prescribed by a list of connected components
- functional blocks that realize signal formation
algorithm block-diagram program models.
At this stage some library modules lacking in
standard tools library must be created. Such library
modules in FPGA structure are called IP-Cores
(Intellectual Property Cores) or IP-functions.
Such modules are universal and reliably repeti-
tive, from the one side, and capable of parametric
adjustment to a particular project, from the other
side. Repeated application of IP-Cores permits
to reduce labor costs and design period of digital
devices, ensuring their high reliability.
Integration of Signal Formation Algorithm
Block-Diagram Program Models in CASE-Tools
Environment:
At that stage signal formation algo-
rithm block-diagram program models as developed
at a previous stage in CASE-tools environment
are integrated. An important issue in this is estab-
lishment of connections and sequences between
developed functional blocks (signal formation
algorithm block-diagram program models), in-
cluding input and output signal formers, in strict
conformity with the developed signal formation
algorithm block-diagrams.
As well as at the previous stage, integration
may be performed both in the form of graphic
diagrams and by programming in hardware de-
scribing language. The result of this stage is a
finite digital device program model ready to be
implemented into FPGA chip.
Implementation of Integrated Program Model
to FPGA Chip:
The developed digital device
logic structure program model is implemented by
adjustment of connections between FPGA logic
cells using the appropriate interface equipment
(JTAG interface) connected to an instrumental
PC. Interface equipment for adjustment of con-
nections between crystal logic cells is selected in
accordance with the type and/or manufacturer of
components applied.
Thus, this step is a transfer from software imple-
mentation of digital device to its final hardware
implementation. The product of this step is an
FPGA-based digital device that performs certain
functions within I&C system.
Verification Approaches for
FPGA Electronic Designs
The conformity between verification stages of
FPGA-projects, tasks performed at those stages
and methods of task performance is explained
in Table 5.
Let us give a short characteristic of FPGA-
projects verification methods.
Documentation Technical Review Method
Applied to Assess Completeness and Correctness
of Algorithm Block-Diagrams:
Signal formation
algorithm block-diagrams are results (products) of
a corresponding FPGA-project development stage.
The completeness of signal formation algorithm
block-diagrams is assessed by comparison between
the lists of developed algorithm block-diagrams
to signal formation conditions according to SRS
agreed with customer. Conformity criterion is co-
incidence between the list of developed algorithm
block-diagrams and signal formation conditions
according to SRS.
Correctness of signal formation algorithm
block-diagrams is assessed by correctness, un-
ambiguous treatment and preparation quality of
the developed block-diagrams. In the course of
analysis the following must be confirmed:
• A separate algorithm block-diagram is pre-
sented for each signal formation condition.
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