Electric Clock for NanoMagnet Logic Circuits - Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives - page 89

This can be done because the intrinsic energy consumption is very small com-
pared to the second source of losses, i.e. the energy loss in the clock generation
network. The biggest contribution to this term of energy consumption is the
energy required to charge the capacitor. Since piezoelectric materials are insula-
tors, every NAND/NOR gate is equivalent to a capacitor (an insulator embraced
by two electrodes). The capacitance can be estimated as shown in Eq. 12 .

C = ʳ 0 · ʳ r · t PZT · h NAND
w NAND

(12)

where ʳ 0 is the absolute dielectric constant, ʳ r is the relative dielectric constant
of the piezoelectric material, t PZT is the thickness of the piezoelectric substrate
while h NAND and w NAND are the NAND/NOR gate height and width. The
voltage that must be applied to every gate can be calculated as in Eq. 13 .

V = w NAND · ˃
Y

(13)

· d 33

where ˃ is the applied stress, Y is the Young modulus of the magnetic material
and d 33 is the coecient that couples the strain and the applied voltage in the
piezoelectric substrate. With this gate sizes and materials, the required voltage is
normally in the range of 0.7-1.3 V. The energy required to charge the capacitance
is then (Eq. 14 ):

E clock = 1

2 · C · V 2

(14)

The bigger it the capacitance, the bigger is the energy consumption. The capac-
itance depends on the physical size of the NAND/NOR gate, like the height and
the width of the island, and in particular it is directly proportional to the piezo-
electric layer thickness. Nevertheless, while physical sizes do not depend on the
particular piezoelectric material used, this is not true for the relative dielectric
constant ( ʳ r ). The capacitance depends directly on the value of ʳ r , so the bigger
it is the bigger the energy consumption is. As can be seen from Table 1 the PZT
ʳ r is quite high, so if this material is used power consumption is expected to
be higher. This is probably the only real flaw of PZT used for this application.
Finally, the value of voltage to be applied depends both on the width of the
island and on physical properties of magnetic and piezoelectric materials used.
Since the geometrical characteristics of every island are determined by logic
constraints (i.e. the number of magnets in the critical path and the structure
of AND/OR gates) and materials are chosen as explained in Sect. 2 , the only
remaining free parameter is the thickness of the piezoelectric layer. Figure 16
indicates the total energy required to switch a NAND/NOR gate, showing the
variation with the PZT thickness. Figure 16 (a) highlights the difference between
the energy consumption and the clock losses in a 3

3 NAND/NOR gate with
magnets made of Terfenol. The intrinsic energy consumption is constant with
different values of PZT thickness, because it depends only on the magnets char-
acteristics. The clock losses increase instead linearly with the PZT thickness and
most important, they are much bigger then the intrinsic energy loss (11000 K b T

×