Electric Clock for NanoMagnet Logic Circuits - Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives - page 87

PATTERNING OF PZT SUBSTRATE THROUGHOUT LITHOGRAPHY

SOLUTION 1:
TOTAL PZT
REMOVAL

V V V

SOLUTION 2:
PARTIAL PZT
REMOVAL

V V V

Fig. 14. Creation of mechanical isolated islands starting from a uniform piezoelectric
layer. The substrate can be patterned with lithography to selectively remove part of it.
The PZT can be removed partially or totally, in both cases a good mechanical isolation
is obtained.

2.4 Performance: Timing and Power Estimation

Recently a dedicated simulator for NML technology, ToPoliNano, was devel-
oped [ 40 , 41 ]. While this tool represents a powerful instrument to automatically
generate [ 42 ] and simulate NML circuits [ 43 ], it does not support low level phys-
ical simulations. To evaluate timing performance of NML circuit it is instead
possible to use low level physical simulators like OOMMF [ 44 ], NMAG [ 45 ]or
Magpar [ 46 ]. These finite element simulators are based on the Landau-Lifshitz-
Gilbert (LLG) equation which describes the dynamic behavior of a generic mag-
netic structure. Among these simulators Magpar allows also the evaluation of
an applied stress on the circuit dynamic. As a consequence, to understand the
timing behavior of the proposed clock system, a NML wire was simulated with
Magpar. Magnet sizes and the value of applied stress are taken from the theo-
retical analysis described in Sect. 2.1 .
Figure 15 shows the simulation results obtained. The reset time, the times
required for a magnet to rotate its magnetization vector from one stable state
to the RESET state, is around 1 ns (Fig. 15 (A)). The switching time, the time
required for a magnet to go from the RESET state to one of the stable states,
is slightly smaller but also in this case it is near 1 ns. This numbers can be used
to estimate the circuits clock frequency. It can be said that in the best case the
clock period must be at least equal to (Eq. 11 ):

T ck = T RESET + N ∗ T SWITCH (11)

T RESET is the reset time, T SWITCH is the switching time and N represents the
number of magnets in the critical path. The critical path is the total number of
magnets in a clock zone between an input to the output. In case of a NAND gate
with a width of 3 magnets, N is equal to 5, therefore the correspondent clock