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A second solution is to deposit the electrodes on top of the piezoelectric
island, as shown in Fig. 11 (D). This solution is technology-friendly, because the
PZT is fabricated before the electrodes, so they are not damaged by the high
temperature processes involved in the PZT fabrication. Moreover, no interface
layer is needed between the electrodes and the substrate. Considering also the
global circuit layout, electrodes placed on top of the substrate are easier to con-
tact. Interconnection wires used to connect the electrodes can be fabricated using
additional layers, in the same ways as CMOS interconnections. This solution is
therefore compatible with CMOS fabrication processes. Magnets are deposited
on the islands after the deposition of the electrodes. This solution shows also a
better electric field distribution (Fig. 11 (E)) than the buried electrodes one. The
electric field is still uniform between the electrodes, moreover near the borders
its intensity increases. Figure 11 (F) shows the electric field lines, similarly to the
previous case they are quite uniform, especially near the surface which is the most
important part. Since the use of electrodes on top of the island shows a better
electric field distribution and is compatible with CMOS fabrication processes,
this is the solution adopted hereinafter for this particular clock system.
B)
A)
Fig. 12. Two possible sizes for the gates. (A) Gates can be 5 magnets width, simplifying
the fabrication processes because the structure is bigger. Performance are however
worse because there are more magnets in the critical path. (B) The minimum gate
width is equal to 3 magnets to grant a proper signal propagation. Performance are
better but higher resolution lithography processes are required.
The electrodes placement is the reason behind the choice of using AND/OR
gates as basic logic gates, instead of using majority voters. Majority voters are
three input gates (see Fig. 2 (C)) where two inputs come from up and down
directions and the central one comes from left direction. The use of a majority
voter with this clock system is therefore not possible, because at the left of
the gate there is one of the electrodes. However AND/OR gates has only two
inputs coming from up and down directions, so there is no interference with
the electrodes. Moreover they are smaller than a majority voter reducing the
circuit area.
The minimum height of the gate is equal to 3 magnets, whilst the width
can be equal to 5 (Fig. 12 (A)) or 3 magnets (Fig. 12 (B)). With 5 magnets
the whole structure is bigger, therefore it is simpler to fabricate. Performance
are worse because there are more magnets on the critical path and therefore the
clock frequency is lower. Furthermore the structure is bigger, so the clock losses
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