Electric Clock for NanoMagnet Logic Circuits - Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives - page 84

NAND GATE
(UNIVERAL GATE = EVERY LOGIC FUNCTION CAN BE IMPLEMENTED)

HELPER BLOCKS

(REDUCE SIGNAL

+

AND INVERTER INPUT1 OUTPUT1 PROPAGATION ERRORS)

LOGIC AND

50 nm

INPUT2

65 nm

PZT

ODD NUMBER OF MAGNETS
HORIZONTALLY COUPLED
(NO SIGNAL INVERSION
IN VERTICALLY
COUPLED MAGNETS)

STRAIN
ELECTRIC FIELD

MAGNET CUT
( ONLY WHEN
BOTH INPUTS ARE )

OUTPUT2

ELECTRODES

INTERDIGITATED

Fig. 10. NAND gate layout. A NAND can be obtained coupling a AND gate [ 17 ]with
an inverter, which is simply made by an odd number of magnets horizontally aligned.

Fig. 11. Electrodes placement. Cell is 350 nm width and the piezoelectric layer is
100 nm thick, while the electrodes section is 50 × 50 nm 2 (A) Electrodes are buried
under the piezoelectric layer. (B) The electric field distribution is quite uniform between
the electrodes (3-4 MV/m with an applied voltage of 1 V) but is lower near the area
correspondent to the electrodes. The strain is proportional to the electric field value.
(C) The electric field lines are quite uniform. (D) Electrodes placed on top of the piezo-
electric island. (E) The distribution is still uniform but the electric field this time is
higher near the two electrodes. (F) Also with this structure the electric field lines have
a good uniformity.

it it 0 directly above them. The strain of the material depends on the electric
field value, so it will be higher in the area between the electrodes and lower
above them. Thanks to the mechanical continuity of the island, there will be
a strain also where the electric field is 0, because, intuitively, the strain of the
central part of the island will induce a strain also near the border of the island.
Electrodes are not exactly placed at the island sides, however, as can be seen
from Fig. 11 (C), the electric field lines distribution is quite good between the
two electrodes, with lines almost parallel to the surface.