Electric Clock for NanoMagnet Logic Circuits - Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives - page 82

Fig. 8. Minimum and maximum stress evaluation changing magnets sizes for (A) Nickel
and (B) Terfenol. As can be seen there is a range where the minimum stress is effectively
lower than the maximum stress, but the range for terfenol is bigger.

2.2 Process Variations

To better understand which of the two proposed materials, Nickel and Terfenol, is
the best candidate for this application, the impact of process variations must be
evaluated as well. The same analysis done before was repeated considering a ran-
dom variation on the shorter magnets side, previously considered fixed at 50 nm.
Figure 9 shows the results. With a process variation of

± 5 % nickel still shows a

good working range (Fig. 9 (A)) but with a variation of 10 % there is just one

value of aspect ratio where magnets can be successfully reset (Fig. 9 (B)). Clearly
with bigger variations, like a

±

20 % variation, there is no working range. Better
results are obtained for terfenol because with a variation of

±

± 5 % (Fig. 9 (D)) and

± 10 % (Fig. 9 (E)) it still shows a good working range. Also considering a varia-

tion of 20 % (Fig. 9 (F)) there is still a value of aspect ratio in which magnets

can be successfully reset.
The consequences are blatant, Terfenol can tolerate higher process variations
than Nickel, making it the best candidate for this application, and it is therefore
used as a reference for the results presented in this chapter. The chosen magnet
sizes are 50

±

10 nm 3 , with an height of 65 nm, correspondent to an aspect
ratio of 1.3, which is exactly in the middle of terfenol working range. These sizes
give therefore the best tolerance to process variations.

× 65 ×

2.3 Building Circuits

To design a generic NML circuit the clock zones layout must comply with two
important requisites:

- It should allow signals propagation in every direction.
- It should take into account the physical constraints of the clock generation
network, i.e. the fabrication and physical placement of the wires used to route
currents or voltages required to implement the multiphase clock system used.