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about an order-of-magnitude better at 100 MHz. The leakage/standby power of the
irreversible mode reaches 1 nW, and the reversible mode around 0.2 nW.
The cost of the adiabatic approach lies in timing and the complicated clocks, since
this design requires eleven clock phases. Adiabatic clocking can recover energy from
the logic circuit, but to achieve system-wide energy efficiency the clock generator
must be able to recycle the energy. Perhaps the most promising approach for energy
recycling is MEMs based resonant clock generators [
23
]. This is a challenge common
to all reversible circuits, including adiabatic CMOS and the QCA.
5.2
Logical Reversibility and Heat Generation
The heat cost of irreversible bit erasures can be approximated and directly related to
the logic gates forming the circuit and the timing of the logic operation. We sum-
marize this for the two operating modes of the designed ALU and predict the limits of
emerging cellular automata circuits.
Irreversible mode of operation. The irreversible mode has the same information loss
as a standard combinatorial static CMOS circuit; for the worst case, an estimate can be
based on the worst-case bit erasures of the underlying gates. Assuming the truth tables
and per-gate erasures in Table
2
, the designed ALU has an upper-bound of logical
information loss of
N
not
R
avg
;
not
þ
N
nand
R
avg
;
nand
þ
N
nor
R
avg
;
nor
þ
N
xor
R
avg
;
xor
85 bits
ð
3
Þ
per arithmetic/logic operation performed, with N
i
the number of each specific gate in
the design and R
avg,j
the weighted average of gate erasures for that gate, with the
parameters for each gate type defined in Table
2
. The per-gate weighted bound is
somewhat pessimistic, since the exact information loss in the logical space depends on
the particular operands, as in the various adders modeled in [
24
]. However, the cor-
responding worst-case information loss heat of E
erasures
= 85 bits 9 0.003 aJ/
bit & 0.250 aJ per arithmetic/logic operation is insignificant, compared to the other
losses in the CMOS circuit, the dissipation of the signal energy and static loss.
Operating at 1 GHz, the information loss heat power is P
erasures
=
(10
9
Hz 91s)9 0.250 aJ = 250 pW in the irreversible mode, which is comparable
to a quarter of the static leakage power using 20 nm technology.
Reversible mode of operation. The Bennett-clocked mode of operation avoids all the
internal bit erasures of the combinatorial ALU structure, leaving only the input
operand words A and B to be erased after the de-computing sequence. With the ALU-
design, this corresponds to the loss of 8 bits, with E
erasures
= 8 bits 9 0.003 aJ/
bit & 0.024 aJ per arithmetic/logic operation, which is an order-of-magnitude better
than the irreversible worst-case bound. However, since the Bennett-clocked structure
has 11 stages, the heat power at 1 GHz clock frequency is P
erasures
=
(10
9
Hz 9 1s)9 0.024 aJ/11 = 2.2 pW in the reversible mode, about 1 % of the
static leakage using 20 nm technology. It should be noted, that also the computing
throughput is only 1/11 of the throughput of the standard implementation at the same
clock frequency.
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