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field correlation factor KAPPA = 0. The effective fast surface state density parameter
was NFS = 0.01, in order to turn on the flow of the subthreshold current. The fol-
lowing directives were used for NMOS and PMOS:
.model nmos nmos LEVEL=3 KP=100u Vt0=0.5 TOX=20n RS=120 RD=120
+VMAX=210k kappa=0 NFS=0.01
.model pmos pmos LEVEL=3 KP=80u Vt0=-0.7 TOX=20n RS=120 RD=120
+VMAX=210k kappa=0 NFS=0.01
In the 20 nm tri-gate technology simulation, the irreversible operation had a
static Clk1…Clk11 = V DD = 0.9 V and Clk1N…Clk11N = GND = 0 V, while the
reversible operation had the swing of the Bennett clocks Clk1…Clk11 between
0-0.45 V and the swing of Clk1N…Clk11N between 0-(-0.45) V. A 20 nm LSTP
transistor model from Arizona State University Predictive Technology Model library
was used [ 22 ]. This is a level 72 model based on the BSIM_CMG model for multi-
gate devices, and we used the default parameter values in the simulation.
5
Design Analysis
The implemented adiabatic CMOS design can be viewed as a prototype of a revers-
ible, locally connected cellular automata based ALU. The Bennett-clocking approach
enables the conservation of signal energy and information in the Landauer/Bennett
meaning. This prototype design was simulated in both modes of operation with
parameters extracted from the devices made at the University of Notre Dame. The
actual 2 lm node chips have been fabricated, but the measurements are ongoing, and
therefore we report only the simulation results here.
5.1
Importance of Adiabatic Operation
The adiabatic charging approach can be very beneficial, since it will minimize the
resistive heat generated by the circuit. The adiabatic CMOS circuit model simulated
with Bennett-type clocking demonstrates that while the logic signal level is very high,
the losses in the circuit can be kept very low. Comparison of irreversible standard
clocking and reversible Bennett-clocking in a 4-bit ALU at the 2 lm node is shown in
Fig. 6 . The reversible mode generally offers two orders-of-magnitude improvement
in average power consumption in the low frequency end up to 3 MHz, and about an
order-of-magnitude improvement up to 50 MHz clock frequency, while the modes are
equal around 200 MHz frequency. Including the parasitic capacitances affects both
modes of operation. The leakage power can be identified in Fig. 6 as the constant
value of power at low frequencies: the irreversible mode has high voltages continu-
ously applied over the transistor drain-source, producing a static level up to 1 mW.
The reversible mode avoids most of the leakage, since the voltages are ramped and
kept at for much of the clock period, producing a static power around 0.01 mW.
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