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Fig. 5. Reversible Bennett-clocking, the dual-rail power-clock waveforms. The design has 11
positive clocks Clk1-Clk11 and 11 negative Clk1_n-Clk11_n, vertically offset for clarity.
an 11-stage 1n1p-type asymptotically adiabatic logic circuit depicted on logic level in
Fig. 3 , where the computing part takes 11 steps and de-computing part 11 steps for
each arithmetic/logic operation. The design in Figs. 3 and 4 contains all the logic
needed for computing and de-computing using the Bennett-clocking scheme, with the
only additional overhead the clock generator not shown. By slowing down the fre-
quency, all of the signal energy can be asymptotically recovered, with no additional
cost in CMOS logic complexity and area. However, the unit is not capable of pipe-
lining, and the generation of the complicated power-clock signals is challenging.
4
Simulation Setup
The irreversible and reversible ALU were simulated in Synopsys HSPICE 2012, in
both the 2 lm and the 20 nm technology. In the 2 lm technology, the irreversible
operation had a static Clk1…Clk11 = V DD = 5 V and Clk1N…Clk11N = GND =
0 V, while the reversible operation had the swing of the Bennett clocks Clk1…Clk11
between 0-2.5 V and the swing of Clk1N…Clk11N between 0-(-2.5) V. A level 3
semi-empirical MOSFET model [ 21 ] with parameters extracted from the devices
made in the fabrication facility at the University of Notre Dame was used, and a 2 lm
gate length was chosen to match the circuits being fabricated. The simulated n-type
transistors had a width/length ratio of 6 lm/2 lm and a threshold voltage of 0.5 V,
while the p-type transistors had a ratio of 12 lm/2 lm and a threshold voltage of -
0.7 V. The gate oxide thickness was 20 nm, and a series resistance of 120 X at both
the drain and the source was included in the model. The intrinsic transconductance
parameter, which is the product of mobility and gate capacitance was KP NMOS =
100 lA/V 2 for NMOS, and KP PMOS = 80 lA/V 2 for PMOS. The velocity saturation
was incorporated into the model by setting the parameter VMAX = 210 k for both
NMOS and PMOS, and the channel length modulation was excluded by setting the
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