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Fig. 4.
The layout of the ALU in 2 lm CMOS.
3.2
Irreversible Standard CMOS Operation
The combinatorial ALU unit can be run in irreversible mode like a standard CMOS
design by setting the power-clock lines to static values, which are held constant
throughout the operation. The positive power-clocks Clk1…Clk11 are tied to the
operating voltage V DD , while the negative power-clocks Clk1N…Clk11N are con-
nected to ground GND. In this configuration, the unit implements a standard com-
binatorial CMOS ALU, without pipelining or any sequential components. This mode
of operation erases information and uses energy exactly like traditional irreversible
CMOS logic.
3.3
Reversible Bennett-Clocked Adiabatic CMOS Operation
The ALU unit can be configured into fully reversible mode by utilizing the dual-rail
power-clock signals with the ramp-up and ramp-down timing defined by the
requirements of Bennett-clocking, setting the signals Clk1-Clk11 and Clk1_n-
Clk11_n to ramp in concatenation as illustrated in Fig. 5 . The design effectively forms
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