Reversible and Adiabatic Computing: Energy-Efficiency Maximized - Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives - page 338

significant circuit design factor [ 2 , 3 ]. With QCA, the irreversibility-induced heat
dissipation may present surprisingly tight operating frequency limits for computer
arithmetic based on high-density nanoscale components. Recent work suggests that
binary adders and multipliers might have maximum operating frequency in tens of
gigahertz instead of hundreds expected of the pipelined designs, with a typical power
density constraint of 100 W/cm 2 [ 4 , 5 ]. While NML circuits do not reach molecular
device densities or gigahertz operating frequencies, their inherent signal energy
conservation suggest use in battery-life limited applications, where the energy dissi-
pated due to information loss could make the difference between a battery life of
months vs. years.
Computer arithmetic circuits represent highly optimized logic designs usually laid
out with extreme care, but the optimization goals have traditionally been the result
latency, throughput, circuit area, or CMOS power. Logical reversibility has not been
one of the goals, and this has the consequence that the existing or proposed arithmetic
circuits are highly sub-optimal from the perspective of information loss. Our recent
study suggests that typical QCA adders generate multiple times the number of bit
erasures than the theoretical minimum for the addition operation [ 6 ], and that QCA
multipliers erase a square-law number of bits vs. operand word length, compared to the
potential sub-linear loss of the theoretical operation [ 7 ]. For an introduction to irre-
versibility induced density and frequency limits in QCA, the reader is referred to [ 8 ].
We believe that logical reversibility is connected to the physical reversibility of
the system, that is, the physical, thermodynamically described state of the system has
to mirror to some degree the computation that is performed. Fifty years ago, Rolf
Landauer proposed this connection in [ 9 ], and finally in 2012, the Landauer's Prin-
ciple was confirmed with a generic one-bit memory experiment [ 10 ]. A bit erasure at
the room temperature has an inevitable energy cost of at least 3 zJ, which must be
dissipated as heat into the environment. To achieve a lower dissipation circuits have to
utilize adiabatic charging in forming the logic or clock signals, and achieve a degree
of logical reversibility. An erasure-aware, partially reversible circuit involves trade-
offs between performance, timing, circuit area, and power, and must balance the
effects of the erasures and adiabatic operation.
This paper explores the tradeoffs in a prototype arithmetic-logic (ALU) unit and is
organized as follows: Sect. 2 gives an introduction into adiabatic circuit operation,
logical reversibility, and the related heat generation. Section 3 describes our adiabatic
transistor circuit, highlighting the challenges and gains of locally connected adiabatic
operation. Section 4 describes the simulation setup and Sect. 5 the corresponding
results on the power consumption. Section 6 presents predictions for the future
technologies, while Sect. 7 the concludes the discussion.

2 Signal Energy Recovery

The energy-efficiency of any integrated circuit technology is closely related to the
method of signal representation and the associated signal energy, which must be larger
than the thermal noise floor by a significant margin [ 1 ]. In standard static CMOS,
every switching event leads to the dissipation of all the signal energy stored on the