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- modification of the logic of one stage to allow the masking of the defects in
the current stage or, alternatively, in the following AND-OR stage;
- addition of wires with function of weak pull-up or pull-down in the device to
maintain at a low logic level inputs potentially faulty (prior to an OR plane),
or at a high logic level (prior to an AND plane);
- joint operation with majority voting circuits based on CMOS at key points of
the architecture.
Nanotiles.
The nanotiles represent the building blocks of NanoArray archi-
tecture. The crossing nanowires form a nanoarray, whose junctions (points of
intersection) can be FETs or not connected. The nanoarrays are surrounded by
microwires, that carry electrical power and, in this particular implementation,
also signals for programming the interconnections. Each signal is present both
in its original form and in complemented form.
Dynamic Pipelining.
Due to design constraints (e.g. doping of the nanowire)
and to topological constraints too, the latches are very dicult to implement
within the nanoarray. Typically, latches or registers are used to obtain the func-
tionalities of pipelining of data streams, for example in a datapath. This com-
ponent is one of the most common within the microprocessor, so it is important
to have an ecient way of pipelining. In NanoArray, when using circuits of the
dynamic type, it is possible to obtain a temporary storage of information, with-
out resorting to the explicit use of a latch. A pipelined NanoArray circuit can be
realized by cascading dynamic nanoTiles, without requiring an explicit latching
of the signals, which would entail a considerable reduction of density. A processor
made in nanotechnology could have thousands of nanoTiles, so it is fundamental
to have an ecient communication system, and this is one of the critical points
in nanoarchitectures. In the NanoArray approach local communication occurs
between nanowires, to maintain an optimum use of the area, while for the global
communications microwires are used.
NanoArray Simulation.
The NanoArray simulation engine belongs to the
class of the event-driven simulators. It follows the information flow inside the
structure under simulation and generates specific events, when necessary, to cor-
rectly handle the propagation of information. To better understand this process,
we can imagine each sub-tile as a four-port device, with each port identified by
a cardinal point.
A change in the information at a given port may need to be propagated inside
the sub-tile, if there is an appropriate component to support propagation (e.g. a
nanowire). We do not need to know anything about the electrical properties of
the component to perform a logical analysis. As a function of the port at which
the change in information happens, and the original direction of propagation
of this piece of information, we can check whether there is support for further
propagation and, if this is the case, to change the information on another port
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