ToPoliNano: NanoMagnet Logic Circuits Design and Simulation - Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives - page 295

Table 1. Simulation performance of two of the most widely used free micromagnetic
tools, NMAG and OOMMF.

Simulator Memory [Mb] Time [s/ns]

4 magnets wire NMAG 49 43

OOMMF 24 89

8 magnets wire NMAG 79 75

OOMMF 32 173

12 magnets wire NMAG 104 127

OOMMF 36 200

of the memory and the simulation time required to simulate a circuit made by
around 2 milions of magnets. For NMAG a total of 12 TB of RAM memory
and 70000 years of simulation time will be required. OOMMF instead requires
only 4 TB of memory and just 35000 years of simulation times. These are just
rough estimations but they clearly show the necessity of using a simulator like
ToPoliNano to handle complex NML circuits. Comparing the performance of
ToPoliNano with Modelsim [ 34 ], one of the most used VHDL simulators is more
complex. However a simple comparison can be obtained looking at the micro-
processor described in [ 26 ] and [ 27 ], or at the systolic array for biosequences
analysis described in [ 55 - 57 ], which are also made by millions of magnets. In that
case the simulation for a time of 100 s required near 1-2 h of machine-time.

Clearly ToPoliNano shows an advantage also over classical VHDL simulators.
Finally the Ripple Carry Adder was used also to test the performance of the
Place & Route block, but only up to 32 bits. Using the most simple cross-wires
minimization techniques, the Barycenter , the creation of the layout required
only 20 ms. Optimizing the layout with the best technique available, the Simu-
lated Annealing , the time required to synthesize a 32 bit adder was equal to few
minutes.

µ

9 General Code Structure

ToPoliNano has been developed in C++ language to be highly ecient in compu-
tation, thus providing ground to study multiple emerging technologies, demand-
ing in terms of computational resources. With regard to the implementation, the
C++ language was selected as programming language mainly for performance
reasons, and the whole structure of the simulation is based on the use of classes
grouped into macro-blocks:

- Controllers, which contains all the high-level logic of the application.
- GUI, which contains all the classes related to the management of graphical
interface (configuration wizard, main window).
- HDL Graph Controller, about the logic of HDL parsing.
- Inputs And Clocks, for the generation of input and clock signals.