ToPoliNano: NanoMagnet Logic Circuits Design and Simulation - Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives - page 288

Fig. 15. Global routing flow diagram. It is an iterative process where the position of
each block for every row is shifted with the aim of minimizing the interconnections
length.
The goal is to find the global minimum area of the circuit, so an iterative app-
roach is needed.
Channel Routing. When the final position of logic gates and pins is defined,
the channel routing routine can start in order to obtain the final layout. In NML
there is a limit to the maximum number of element that can be cascaded inside
a clock zone. This feature coupled with the clock zones layout makes the signals
propagation follow a “stair-like” path, as shown in Fig. 4 (B). To model this
behavior the channel routing algorithm is based on the mini-swap [ 49 ] method,
which uses diagonal interconnections. Again though based on these algorithm,
the method is a mix and largely adapted to the NML case.
Circuit Example. Figure 16 shows an example of circuit obtained after the
whole process. It is a 6 bits ripple carry adder where the zoomed element repre-
sents a cross wire block.
References. The literature about placement and routing of VLSI circuits is
quite wide. For interested readers an overview of the automatic placement and
routing of CMOS VLSI circuits can be found in [ 50 , 51 ]. More detail on the wire
and channel routing can instead be found in [ 49 , 52 - 54 ].