ToPoliNano: NanoMagnet Logic Circuits Design and Simulation - Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives - page 281

VHDL GRAMMAR

ENTITY
DECLARATION

ARCHITECTURE
BODY

ARCHITECTURE
DECLARATIVE
PA R T

ARCHITECTURE
STATEMENT PART

COMPONENT
DECLARATION

SIGNAL
DECLARATION

GENERATE
STATEMENT

GENERIC MAP
AND PORT MAP

SIGNAL
ASSIGNMENT

PORT CLAUSE GENERIC CLAUSE

Fig. 9. Hierarchy of VHDL Grammar.

ENTITY ARCHITECTURE

VHDL DATA STRUCTURE

Fig. 10. VHDL Design Entity Data structure.

tool. Up to now, the Parser just recognizes data, but does nothing with it. A
dynamic data structure is built and instantiate at runtime dynamic objects of
certain classes just when they are needed, and populate them at parse time. The
data structure used to store the parsed information from a VHDL design unit is
a dynamic object of a main class called VhdlClass, which comprises pointers to
an Entity object and to an Architecture object. It is shown in Fig. 10 .

3.6 Intermediate Form Representation

Once all the VHDL design units have been parsed, a data structure that repre-
sents the digital circuit, component by component, has to be implemented. The
idea is to create a hierarchical graph of nodes that represents the circuit and all