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more than the previous case, hence
; this increase is also reflected in the
denominator of formula ( 8 ) as an increase in total time. Moreover,
l
=
nM
J
must be re-evaluated considering interleaving. SAs performance are often eval-
uated computing peak CUPS max(
Z cell
and
is the
number of PEs in the array. Equation 8 is more precise and takes into account
the effects of interconnections and delays inside PEs. This equation is upper
bounded by max(
CUPS
)=
f clk ×
#
PEs
where #
PEs
).
In order to demonstrate the effectiveness of the proposed mechanism of
pipeline interleaving to increase performance, we evaluated CUPS according to
( 8 ) for different levels of interleaving in a practical case. Hereinafter values are
given in number of clock cycles. Consider a WIL-S SA with
CUPS
Z e
=8,
Z fo =7,
Z fb = 5, with
Z fo that cannot be further pipelined, while the feedback
can be represented as a shift register. Without interleaving
Z e
and
Z cell =
Z e +
Z fo =15
and
= 10 whatever the level of interleaving,
since this value is not influenced by interleaving. In this case Eq. 8 reduces to:
CUPS
J
=
Z loop
= 12. Moreover, let
S
3
=
M
/
(32
M −
17). It is possible to achieve interleave 2 considering that
J
= 8 so it is required to design the feedback loop to have a
delay of 12 clock cycles. In this case Eq. 8 must be adapted considering
= max
{Z e ,Z fo }
J
=8
and
for different
levels of interleaving. It can be immediately noticed that applying interleaving
results in significant benefits in terms of CUPS. Moreover, it is evident that
benefits of applying interleaving saturate with deeper levels of interleaving.
P
=2
M
. Figure 25 shows the trend of CUPS in function of
M
Fig. 25. The effect of pipeline interleaving on CUPS: given an array of M × M cells,
increasing the level of interleaving CUPS increase as well.
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