NanoMagnet Logic: An Architectural Level Overview - Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives - page 234

Fig. 13. MAC simulations, with inputs sent one every 52 clock cycles (A) and every 50
clock cycles (B). If the delay between new inputs is lower than the loop length errors
are generated.
deeper, it depends on the circuit layout and it is not a pure designers choice.
Solutions to improve performance in circuits with loops are presented in Sect. 3.1 .
The second problem encountered with loops in intrinsically pipelined circuits,
is related to signals synchronization if more loops are present inside the circuit.
Synchronization problems and related solutions are presented in Sect. 3.2 .
3.1 Throughput Maximization
To maximize performance two possible approaches can be used. It is possible to
work at algorithmic level, rearranging data avoiding data dependencies, or it is
possible to work on the circuit architecture with the aim of reducing the loops
length. In the following both solutions are presented.
Interleaving. As seen above, if a loop is present, two consecutive data operands
can only be sent to the system after a number of clock cycles equal to the loop
length degrading system performance. The reason for this problem lies in the
fact that there is data dependencies between two consecutive data, i.e. one data
depends on the previously sent data. It is however possible to work at algorith-
mic level rearranging data to avoid data dependencies. To do so, some tech-
niques that are commonly adopted in CMOS technology can also be applied
here, like dynamic data dependency rearrangements and predictive techniques
used in superscalar microprocessors. These solutions may potentially improve
performance. However they aggravate the system with additional calculations,
and require careful effectiveness analysis from application to application. A more
simple technique, called “interleaving”, can be adopted. It does not require sig-
nificant modifications to the original algorithm. The basic concept of interleaving
is to parallelize relatively independent operations by interleaving data sequence
at the inputs. As an example two independent sequences of data A, B and C, D