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improved asynchronous protocol only 0.546
s are required. As a consequence
a speed up of 10 times can be observed. This result demonstrates the validity
of the logic solution here proposed, which allows to solve the layout=timing
problem without speed penalties. The clock frequency used in the simulation
is about 100 MHz, that means a clock period of about 10 ns. The execution of
one instruction with the improved logic requires therefore 53 clock cycles. This
slowdown is not due to the use of asynchronous logic but to the presence of
a long feedback signals inside the circuit. This aspect is described in detail in
Sect.
3
.
ยต
2.2 Clock Zones Layout for Automatic Signals Synchronization
In order to synchronize signals in a complex circuit it is however possible to
work on the clock zones layout instead that on the logic type. The idea is to
exploit the potential of circuit layout shown in Fig.
4
(A). A circuit detailed
example is reported in Fig.
11
. Clock zones are made by parallel strips and
inputs arrive from the left side, all of them starting from the first clock zone.
Output signals are generated at the circuit right side. With these constraints,
perfect signals synchronization is achieved. At any point inside the circuits all
signals are perfectly synchronous. This result is obtained without the need of
using asynchronous logic keeping the circuit as simple as possible, minimizing
the area overhead and maximizing performance. Moreover this solution allows to
gain two further advantages. Signals synchronization is automatically achieved
independently of circuit complexity and this approach can be successfully applied
for hierarchical circuit descriptions.
While the clock zones layout of Fig.
11
was built upon the constraints of NML
circuits based on magnetic field clock, it allows other considerable results to be
achieved, like automatic signals synchronization and easy circuits description.
As a consequence this same layout can be exploited also for other clock systems.
Its regularity also greatly helps the fabrication process.
3 Loops
If the pipelined nature of these technologies causes troubles to achieve signals
synchronization in combinational circuits, the situation worsens when loops are
present inside the circuit. Loops are required to build any complex circuit. An
example of such a system is reported in Fig.
12
, where the detailed layout of a
2 bits multiply and accumulate unit (MAC) is shown. In Fig.
12
the simplified
circuit schematic is reported in detail. Two incoming signals are multiplied and
then the result is added to the result of the previous operation. MAC units are
a fundamental block in digital signals processors (DSP).
The first and most important problem due to the presence of loops is the loss
of performance. In pure combinational circuits thanks to the pipelining a new
data can be sent to the circuit every clock cycle. If a loop of length N clock cycles
is present, a new input can be sent only every N clock cycles, thus reducing the
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