NanoMagnet Logic: An Architectural Level Overview - Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives - page 230

As a consequence in [ 41 ] we have developed a new mixed synchronous-
asynchronous protocol to exploit the maximum potential from this technology.
The protocol is described in Fig. 9 . It is based on simple boolean logic gates with
no signals encoding, greatly reducing the area overhead. Asynchronous registers
are substituted by a synchronization block shown in Fig. 9 , which is simply a mul-
tiplexer with the output connected to one of its inputs. Normally the Selection
bit ( Sel in Fig. 9 ) is at logic '0', that means that the multiplexer is in memory
state and its output is constant. Every N clock cycles a new data is sent to the
multiplexer input followed by an enable signal which is connected to the Sel pin
of the multiplexer. As a consequence the multiplexer samples the new data and
after it returns in the memory state. The consequence is that a new data is sent
to the circuit every N clock cycles and in the middle the output value of the
multiplexer is kept constant. The value of N is chosen according to the longest
propagation delay in the combinational path (in case of Fig. 9 it is equal to 2
clock cycles) in this way all signals have time to propagate through the circuit,
granting a correct operation of the circuit.
Fig. 9. New asynchronous protocol. No signal coding is used and asynchronous registers
are substituted by a multiplexer with the output connected to one of its inputs. The
output of the multiplexer is kept constant and only every N clock cycles a new data is
sampled. The value of N is chosen according to the maximum propagation delay in the
combinational path, in order to ensure that all signals had time to propagate correctly
through the circuit.
To evaluate the performance of different logic solutions a simple but com-
plete microprocessor was developed in [ 32 , 41 ]. The microprocessor is schemati-
cally reported in Fig. 10 (A). The architecture is based on four main components,
a program counter to run programs, two memories, one for instructions and
one for data, and an arithmetic-logic unit to execute the selected instruction.
Asynchronous registers are exploited to implement the communication protocol.
The microprocessor architecture is simple but it allows to execute all kind of
instructions commonly found in the instruction set of commercially available