NanoMagnet Logic: An Architectural Level Overview - Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives - page 228

at logic level and one at layout level. The first solution, described in Sect. 2.1 ,
is based on the use of delay insensitive asynchronous logic to obtain automatic
signals synchronization. The second solution, described in Sect. 2.2 , is based on
the introduction of constraints on the clock zones layout making it very regular
and automatically equalizing the length of every wire in the circuit.

2.1 Asynchronous Logic

The first solution that can be adopted to solve the “layout=timing” problem
is to use a different kind of logic, particularly a specific type of asynchronous
logic called Null Convention Logic (NCL). In this logic [ 39 , 40 ] signals are coded
using two bits (Fig. 7 (A)). The logic '0' corresponds to the coding '01' while logic
'1' corresponds to the coding '10'. '00' corresponds to a particular state called
NULL. '11' is a not allowed state. Figure 7 (B) shows an example of NCL gate,
called TH22, and its logic equation. The particularity of this kind of logic is that
it is completely delay insensitive. The circuit behavior is depicted in Fig. 7 (C).
Circuits switch periodically from DATA to NULL and from NULL to DATA,
however the transition happens only when all inputs switch. This means that
circuit will switch from NULL to DATA only when all inputs switch from NULL
to DATA. Circuits will remain in the DATA state until at least one of the inputs
is in the DATA state. The transition from DATA to NULL will happen only
if and when all inputs will switch from DATA to NULL. Then the cycle will
restart. As a consequence a complete delay insensitivity is reached, because it
does not matter if there is a difference in the propagation delay of signals. The
transition from one state to the other will occur only when the last signal arrives
at the circuit inputs.

A B

TH22

A

00 NULL

F

DATA 0

01

2

B

DATA 1

10

11 NOT ALLOWED

F=A*B+F(A+B)

C)

01 or 10

01 or 10 00 01 or 10 00

DATA NULL DATA NULL DATA

Fig. 7. Null Convention Logic (NCL). (A) Signals are coded using two bits. (B) Exam-
ple of NCL gate and its logic equation. (C) NCL circuits switch periodically from DATA
to NULL state and then from NULL to DATA.

The delay insensitivity of NCL logic apparently makes it perfect for NML
circuits. This solution works correctly as demonstrated in [ 32 , 41 ], but it greatly
reduces circuits performance. This also happens if CMOS technology is used
as a target, because the high robustness of this logic comes at the price of