NanoMagnet Logic: An Architectural Level Overview - Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives - page 227

It is important to further underline that while the results here presented are
obtained using NanoMagnet Logic as a target technology, they can be applied
to any Field-Coupled device. This chapter shows therefore the guidelines that a
designer should follow to effectively develop circuits with this technology. These
guidelines are also used in ToPoliNano [ 34 - 36 ] a dedicated synthesis/simulation
tool for NML that we are developing. As part of ToPoliNano we are working on
an automatic layout generator [ 37 ] that is necessary based on the rules presented
in this chapter.
2 Layout=Timing
The first important problem that a designer must face during the development of
any NML circuit is called “layout=timing” [ 33 ]. Thanks to the multiphase clock
system, every group of N consecutive clock zones has a delay of exactly one clock
cycle. The main consequence is that the propagation delay is no more a designer
choice but it depends on the circuit layout. However, synchronization issues can
arise due to mismatch in the wires length and therefore in the propagation delay
of signals. The situation is explained in Fig. 6 . Two input wires are connected
to a NML AND gate. AND/OR gates can be obtained changing the shape of
one magnets as shown in [ 31 ], and altogether with the majority voters [ 30 , 38 ]
and inverter they represent the logic gates set available with this technology. In
Fig. 6 (A) input wires have a different length in terms of clock zones. The two
input signals arrive at the gate inputs with the difference of one clock cycle and
the output of the gate is consequently wrong. To solve this problem the wires
length must equalized, as shown in Fig. 6 (B). Signals are therefore perfectly
synchronized and the gate output is correct.
Fig. 6. Layout=Timing problem. Since the propagation delay of a signal depends on
the wires length, if input wires of one gate have different lengths, their signals will arrive
with different delays and the result will be wrong. Wires length must be equalized to
synchronize signals and obtain the correct result.
Nonetheless, considering a complex circuit based on hundreds of thousands
or millions of gates, the equalization of the length of every signal in it can be a
nearly impossible task. In the following we discuss two different solutions, one