NanoMagnet Logic: An Architectural Level Overview - Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives - page 226

therefore to an intrinsic pipelined behavior. Pipelining is a common feature also
in CMOS technology but in this case there are two important differences. In
CMOS the level of pipelining is generally small and moreover it is a parameter
chosen by the designer. In this case the level of pipelining is extremely high and
it is not a parameter chosen by the designer but it depends on the circuit layout
[ 33 ]. This is valid for all the clock implementations, also in case of the Out-of-
plane NML clock (Fig. 3 (D)). While with this clock system no clock zones exists,
in a wire signals needs exactly one clock cycle to propagate through two magnets
[ 27 ]. As a consequence a block of two magnets in a wire has a delay of one clock
cycles.

D ELAY = 1 CLOCK CYCLE

DELAY = 2 CLOCK CYCLES

SWITCH RESET HOLD SWITCH RESET HOLD SWITCH RESET HOLD

R

R R

E

E E

G

G G

Fig. 5. NML intrinsic pipelining. Every group of 3 consecutive clock zones has a delay
of 1 clock cycle and is therefore equivalent to a CMOS register.

In Field-Coupled technologies, like QCA and NML, three important problems
can be identified at the architectural level. Some of them are already known. Here
we assess them and we discuss thoroughly several alternative solutions, some of
them previously mentioned and some newly proposed here.

- LAYOUT=TIMING . This is the first problem that arises thanks to the intrin-
sic circuits pipelining. The propagation delay of a signal in terms of clock
cycles depends on the length of its correspondent wire in terms of clock zones.
As a consequence mismatches in the wires length generates errors in the logic
operations performed by the circuit. This problem is analyzed in detail in
Sect. 2 .
- LOOPS . This is the second problem due to the intrinsic pipelining. If a loop
with a length of N clock cycles is present inside the circuit, the throughput
is reduced of N times. Moreover serious synchronization problems arise. This
problem is thoroughly studied in Sect. 3 .
- INTERCONNECTIONS . This further issue is connected to both the Field-
Coupling principle that represents the base of this technology, and to its
intrinsic pipelining. In complex circuits interconnections occupy a lot of area,
moreover long interconnections generate a long delay in signals propagation.
This problem is described in Sect. 4 .