NanoMagnet Logic: An Architectural Level Overview - Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives - page 225

quite limited [ 14 , 28 ]. As a consequence vertical signals follow a stair-like prop-
agation (see Fig. 4 (A)). This clock system is called “snake clock” because the
vertical signals propagation recalls the movement of a snake. To propagate sig-
nals in the opposite direction, from right to left it is instead necessary to switch
the order of phase 2 and 3. This is possible locally twisting the correspondent
wires as shown in Fig. 4 (B). Wires are physically located on different planes [ 13 ]
so they can be twisted freely without interferences. Magnets cannot be placed
in the area correspondent to the clock wires crossing. We have demonstrated in
[ 29 , 30 ] that this clock system is immune to possible crosstalk between neighbor
clock wires.
Fig. 4. Snake clock system. (A) Clock zones are made by parallel strips that correspond
to the clock wires used to generate the magnetic field. (B) To allows signals propagation
wires are twisted when signals need to propagate in different directions. The wire twist-
ing is possible because wires are alternatively placed over and under magnets plane.
Other clock solutions are possible, for example in [ 31 ] a more simple 2-phases
clock was presented. Moreover other clock systems will have different clock con-
straints. However two important things must be understood: first, the clock
zones layout must be chosen carefully according to the technological processes
used to fabricate the clock generation network and to the requirements of the
NML signals propagation. The second important fact to be considered are the
constraints and limitations generated by the chosen clock system, that must be
carefully taken into account in the circuits design. More in general this is true
also for other QCA implementations.
1.2 Problems and Solutions
While the clock mechanism influences the circuits layout differently, depending
on the particular system chosen, it has a second more important consequence
that is shared by all kind of NML and QCA implementations. Considering a
N-phase clock system, every group of N consecutive clock zones has a delay
of exactly one clock cycles and it is therefore equivalent to a CMOS register
(Fig. 5 ). A QCA wire can therefore be seen as a shift register [ 18 , 32 ], leading